Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
Hardware Security
biblio
Area Constraint Aware Physical Unclonable Function for Intelligence Module
Submitted by
grigby1
on Mon, 12/09/2019 - 1:01pm
area constraint aware physical unclonable function
area constraint aware PUF
artificial intelligence technology
Artificial Neural Networks
authentication
authentication techniques
circuit area
composability
Compositionality
computational intelligence
Cryptography
edge computing
field programmable gate arrays
Hamming distance
Hardware
Hardware Security
intelligence module
IoT devices
neural network
Neurons
NN
Physical Unclonable Function
physical unclonable functions
pubcrawl
PUF performance evaluation
security countermeasures
security of IoT device
Table lookup
biblio
Semantics-Directed Prototyping of Hardware Runtime Monitors
Submitted by
grigby1
on Mon, 11/04/2019 - 11:35am
Biomedical monitoring
building memory protection mechanisms
composability
embedded hardware
embedded processor
embedded systems
formal verification
Hardware
hardware monitor
hardware runtime monitors
Hardware Security
hardware-based protection
high level synthesis
Human behavior
Human Factors
Instruction sets
Model driven development
Monitoring
multiple memory accesses
pubcrawl
rapid-prototyping runtime monitors
reconfigurable architectures
resilience
Resiliency
rop attacks
ROP-style code reuse attacks
Runtime
Scalability
security of data
Semantics
semantics-directed prototyping
software monitor
software-based attacks
biblio
Hardware Implementation of Dynamic Key Value Based Stream Cipher Using Chaotic Logistic Map
Submitted by
grigby1
on Tue, 10/08/2019 - 3:44pm
asymmetric key chaos based cryptography
binary sequence
binary sequences
chaos
Chaos based cryptography
chaotic logistic map
Ciphers
dynamic key value based stream cipher
embedded systems
field programmable gate arrays
Field programmable gated array
FPGA device
frequency 62.2 MHz
Hardware
Hardware Security
hardware-based embedded system
Human behavior
key scheduling
key stream
logistic map
Logistics
Metrics
NIST statistical
nonrecursive key
private key cryptography
PRNG
pseudorandom number generation
pseudorandom sequence generation
pubcrawl
public key cryptography
random key generation
random number generation
Random sequences
randomness tests
resilience
Resiliency
Scalability
stream cipher
symmetric key chaos based cryptography
Thermal analysis
Verilog HDL
X-power
Xilinx device
biblio
Repurposing SoC Analog Circuitry for Additional COTS Hardware Security
Submitted by
grigby1
on Wed, 09/11/2019 - 1:44pm
ADC
additional COTS hardware security
analog to digital converters
analogue-digital conversion
commercial off-the-shelf system-on-a-chip integrated circuits
common COTS microcontroller
comparators
composability
COTS security
Cryptography
DAC
device authentication activities
digital to analog converters
digital-analogue conversion
encryption
Hardware
Hardware Security
Metrics
microcontrollers
Microelectronics Security
on-chip analog blocks
on-chip analog hardware blocks
physically unclonable function responses
processing algorithms
pubcrawl
PUF responses
reliable key generation
repurposing SoC analog circuitry
resilience
Resiliency
security
Semiconductor device measurement
system-on-chip
temperature fluctuations
Temperature measurement
trusted microelectronics
biblio
FPGA-oriented moving target defense against security threats from malicious FPGA tools
Submitted by
aekwall
on Mon, 09/09/2019 - 9:48am
security of data
field programmable gate arrays
FPGA
Hardware
security
Table lookup
Resiliency
pubcrawl
Trojan horses
security threats
Hardware Security
Scalability
Benchmark testing
moving target defense
defense lines
FOMTD
FPGA configuration
FPGA design suite
FPGA emulation results
FPGA hardware-software providers
FPGA security
FPGA users
FPGA-oriented MTD method
hardware trojan
malicious FPGA tools
moving target defense principle
reverse engineering
target defense
Xilinx
Predictive Metrics
biblio
HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security
Submitted by
grigby1
on Thu, 09/05/2019 - 10:27am
composability
Control Theory
Hardware Security
information-flow security
pubcrawl
resilience
Resiliency
security
timing channels
biblio
Solving Internet's Weak Link for Blockchain and IoT Applications
Submitted by
aekwall
on Mon, 08/26/2019 - 9:07am
security weaknesses
SECP256K1
resilience
pubcrawl
Private keys
policy-based governance
Metrics
Key storage
IoT
Internet of Things
Human behavior
Hardware Security
encryption
Digital signing
Decentralized Security
Cryptography
blockchain
authentication
biblio
A Unifying Logic Encryption Security Metric
Submitted by
aekwall
on Mon, 07/01/2019 - 9:14am
obfuscation
logic encryption
Security Metrics
Hardware Security
Metrics
pubcrawl
biblio
Property Specific Information Flow Analysis for Hardware Security Verification
Submitted by
grigby1
on Mon, 05/20/2019 - 3:30pm
Control Theory
security
Acceleration
collaboration
Complexity theory
composability
Design methodology
formal verification
Hardware
hardware information flow analysis
Hardware Security
hardware security verification
hardware security vulnerabilities
Hardware Trojans
Human behavior
Human Factors
information flow analysis
information flow models
information flow security
information theoretic security
Mathematical model
Metrics
policy-based governance
potential security violations
property specific information flow analysis
property specific search
property specific trimming technique
pubcrawl
resilience
Resiliency
Scalability
security critical paths
security model
security of data
security property
security verification
timing
Trojan horses
unintended design flaws
biblio
A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks
Submitted by
grigby1
on Fri, 04/05/2019 - 9:29am
Chained Attacks
Clocks
Controllability
Cryptography
design for test technology
design for testability
Discrete Fourier transforms
dynamic key generation
dynamic-key secure DFT structure
dynamic-key secure scan structure
flip-flops
Generators
Hardware Security
integrated circuit testing
memory attack
memory attacks
memory cold boot attack
pubcrawl
Random access memory
resilience
Resiliency
Scalability
scan design key generator
secure scan architecture
security
security level
side channel attack
Side-channel attack
1
2
3
4
5
6
next ›
last »
