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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
Hardware Security
biblio
Hardware Implementation of Dynamic Key Value Based Stream Cipher Using Chaotic Logistic Map
Submitted by
grigby1
on Tue, 10/08/2019 - 4:44pm
asymmetric key chaos based cryptography
binary sequence
binary sequences
chaos
Chaos based cryptography
chaotic logistic map
Ciphers
dynamic key value based stream cipher
embedded systems
field programmable gate arrays
Field programmable gated array
FPGA device
frequency 62.2 MHz
Hardware
Hardware Security
hardware-based embedded system
Human behavior
key scheduling
key stream
logistic map
Logistics
Metrics
NIST statistical
nonrecursive key
private key cryptography
PRNG
pseudorandom number generation
pseudorandom sequence generation
pubcrawl
public key cryptography
random key generation
random number generation
Random sequences
randomness tests
resilience
Resiliency
Scalability
stream cipher
symmetric key chaos based cryptography
Thermal analysis
Verilog HDL
X-power
Xilinx device
biblio
Repurposing SoC Analog Circuitry for Additional COTS Hardware Security
Submitted by
grigby1
on Wed, 09/11/2019 - 2:44pm
ADC
additional COTS hardware security
analog to digital converters
analogue-digital conversion
commercial off-the-shelf system-on-a-chip integrated circuits
common COTS microcontroller
comparators
composability
COTS security
Cryptography
DAC
device authentication activities
digital to analog converters
digital-analogue conversion
encryption
Hardware
Hardware Security
Metrics
microcontrollers
Microelectronics Security
on-chip analog blocks
on-chip analog hardware blocks
physically unclonable function responses
processing algorithms
pubcrawl
PUF responses
reliable key generation
repurposing SoC analog circuitry
resilience
Resiliency
security
Semiconductor device measurement
system-on-chip
temperature fluctuations
Temperature measurement
trusted microelectronics
biblio
FPGA-oriented moving target defense against security threats from malicious FPGA tools
Submitted by
aekwall
on Mon, 09/09/2019 - 10:48am
security of data
field programmable gate arrays
FPGA
Hardware
security
Table lookup
Resiliency
pubcrawl
Trojan horses
security threats
Hardware Security
Scalability
Benchmark testing
moving target defense
defense lines
FOMTD
FPGA configuration
FPGA design suite
FPGA emulation results
FPGA hardware-software providers
FPGA security
FPGA users
FPGA-oriented MTD method
hardware trojan
malicious FPGA tools
moving target defense principle
reverse engineering
target defense
Xilinx
Predictive Metrics
biblio
HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security
Submitted by
grigby1
on Thu, 09/05/2019 - 11:27am
composability
Control Theory
Hardware Security
information-flow security
pubcrawl
resilience
Resiliency
security
timing channels
biblio
Solving Internet's Weak Link for Blockchain and IoT Applications
Submitted by
aekwall
on Mon, 08/26/2019 - 10:07am
security weaknesses
SECP256K1
resilience
pubcrawl
Private keys
policy-based governance
Metrics
Key storage
IoT
Internet of Things
Human behavior
Hardware Security
encryption
Digital signing
Decentralized Security
Cryptography
blockchain
authentication
biblio
A Unifying Logic Encryption Security Metric
Submitted by
aekwall
on Mon, 07/01/2019 - 10:14am
obfuscation
logic encryption
Security Metrics
Hardware Security
Metrics
pubcrawl
biblio
Property Specific Information Flow Analysis for Hardware Security Verification
Submitted by
grigby1
on Mon, 05/20/2019 - 4:30pm
Control Theory
security
Acceleration
collaboration
Complexity theory
composability
Design methodology
formal verification
Hardware
hardware information flow analysis
Hardware Security
hardware security verification
hardware security vulnerabilities
Hardware Trojans
Human behavior
Human Factors
information flow analysis
information flow models
information flow security
information theoretic security
Mathematical model
Metrics
policy-based governance
potential security violations
property specific information flow analysis
property specific search
property specific trimming technique
pubcrawl
resilience
Resiliency
Scalability
security critical paths
security model
security of data
security property
security verification
timing
Trojan horses
unintended design flaws
biblio
A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks
Submitted by
grigby1
on Fri, 04/05/2019 - 10:29am
security
resilience
pubcrawl
Scalability
Hardware Security
Cryptography
Random access memory
Discrete Fourier transforms
Side-channel attack
Generators
Controllability
Clocks
design for testability
secure scan architecture
Resiliency
integrated circuit testing
design for test technology
dynamic key generation
dynamic-key secure DFT structure
dynamic-key secure scan structure
flip-flops
memory attack
memory attacks
memory cold boot attack
scan design key generator
security level
side channel attack
Chained Attacks
biblio
SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures
Submitted by
aekwall
on Mon, 03/25/2019 - 9:57am
Resiliency
pubcrawl
composability
Metrics
Process Variations
Hardware Security
photonic NoCs
signal processing security
biblio
A Co-Training Based Hardware Trojan Detection Technique by Exploiting Unlabeled ICs and Inaccurate Simulation Models
Submitted by
grigby1
on Fri, 03/15/2019 - 11:59am
accurate classification model
actual silicon fabrication
Classification algorithms
classification-based golden chips-free hardware Trojan detection technique
co-training
co-training based hardware Trojan detection technique
fabricated golden chips
fabrication
golden chip
Hardware
Hardware Security
hardware Trojan detection
IC labeling
inaccurate simulation models
Integrated circuit modeling
invasive software
learning (artificial intelligence)
pattern classification
pubcrawl
reliable detection capability
Silicon
simulated IC
Training
trojan horse detection
Trojan horses
unlabeled fabricated IC
unlabeled IC
unlabeled ICs
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