International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2016) The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) is the premier event in system-level design, modeling, analysis, and implementation of modern embedded and cyber-physical systems, from system-level specification and optimization down to system synthesis of multi-processor hardware/software implementations.

14th International Workshop on Real-Time Networks (RTN 2016) PRESENTATION The Real-Time Networks (RTN) is a satellite workshop of the 28th Euromicro Conference on Real-Time Systems (ECRTS 2016), the premier European venue for presenting research into the broad area of real-time and embedded systems. The RTN 2016 workshop is the fourteenth in the series of workshops that started at the 2002 ECRTS conference. No edition took however place in 2015.

LEAD PI TITLE (with link to Poster and Abstract) VIDEO

2nd INTERNATIONAL WORKSHOP ON SOFTWARE ENGINEERING FOR SMART CYBER-PHYSICAL SYSTEMS (SEsCPS) In conjunction with ICSE 2016 May 14-22, 2016 | Austin, TX, USA) | http://d3s.mff.cuni.cz/conferences/sescps2016/ INTRODUCTION

Abstract: The PIs are developing their novel modeling paradigm, Generalized Synchronization Trees (GSTs), into a rich framework for both describing cyber-physical systems (CPSs) and studying their behavior under interconnection. GSTs were inspired by Milner’s use of Synchronization Trees (STs) to model interconnected computing processes, but GSTs generalize the mathematical structure of their forebears in such a way as to encompass many classes of CPSs.

Abstract: The research objective of this project is to bridge two disparate paths to the control of hybrid dynamical systems—namely, symbolic model-based and Lyapunov analysis-based approaches—via convex programming in order to address major challenges in hybrid control. The primary goal is to establish nonconservative, robust, and scalable control theories and algorithms for verifying/achieving desired stability and performance bounds for hybrid affine systems.