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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
Table lookup
biblio
Resilient Reorder Buffer Design for Network-on-Chip
Submitted by
grigby1
on Fri, 03/27/2020 - 11:27am
area efficient safe design techniques
buffer circuits
collaboration
control logic function
Diagnostic Coverage requirement
error correction codes
error detection
error detection code
error detection codes
fault tolerance
Fault tolerant systems
high performance computing systems
Human behavior
Human Factors
Industries
integrated circuit design
invariance checking
logic design
Metrics
Network interfaces
network-on-chip
Network-on-Chip Advanced eXtensible Interface Network Interface block
parallel processing
policy-based governance
pubcrawl
random control logic
Registers
Reorder Buffer
resilience
Resiliency
resilient Reorder buffer design
Safe Coding
safe control logic design
safe ROB design
Safety
Table lookup
biblio
Hardware implementation of Piccolo Encryption Algorithm for constrained RFID application
Submitted by
aekwall
on Mon, 02/10/2020 - 11:44am
IoT
field programmable gate arrays
FPGA
Cryptography
encryption
Internet of Things
telecommunication security
Hardware
Table lookup
IoT applications
smart devices
Resiliency
pubcrawl
composability
security applications
RFID
Throughput
Ciphers
security issues
Predictive Metrics
private information
word length 128.0 bit
Hardware Implementation
hardware resources
lightweight cryptographic algorithms
S-box
lightweight cryptography
128 bits
4 input LUTs
64 bits block size
area optimization
ASIC
constrained RFID application
different design strategies
efficient hardware architecture
Fiestel structure
hardware design
hardware metrics
low resource applications
optimized area
Piccolo Algorithm
piccolo encryption algorithm
piccolo lightweight algorithm
radiofrequency identification
relevant lightweight block ciphers
severe security concerns
supports high speed
Throughput.
tremendous pace
ultra-lightweight applications
variable key size
word length 64.0 bit
word length 80.0 bit
Xillinx
Microelectronics Security
biblio
Area Constraint Aware Physical Unclonable Function for Intelligence Module
Submitted by
grigby1
on Mon, 12/09/2019 - 2:01pm
area constraint aware physical unclonable function
area constraint aware PUF
artificial intelligence technology
Artificial Neural Networks
authentication
authentication techniques
circuit area
composability
Compositionality
computational intelligence
Cryptography
edge computing
field programmable gate arrays
Hamming distance
Hardware
Hardware Security
intelligence module
IoT devices
neural network
Neurons
NN
Physical Unclonable Function
physical unclonable functions
pubcrawl
PUF performance evaluation
security countermeasures
security of IoT device
Table lookup
biblio
FPGA-oriented moving target defense against security threats from malicious FPGA tools
Submitted by
aekwall
on Mon, 09/09/2019 - 10:48am
security of data
field programmable gate arrays
FPGA
Hardware
security
Table lookup
Resiliency
pubcrawl
Trojan horses
security threats
Hardware Security
Scalability
Benchmark testing
moving target defense
defense lines
FOMTD
FPGA configuration
FPGA design suite
FPGA emulation results
FPGA hardware-software providers
FPGA security
FPGA users
FPGA-oriented MTD method
hardware trojan
malicious FPGA tools
moving target defense principle
reverse engineering
target defense
Xilinx
Predictive Metrics
biblio
Securing Mobile Data Collectors by Integrating Software Attestation and Encrypted Data Repositories
Submitted by
aekwall
on Wed, 02/13/2019 - 11:58am
security of data
encryption
data privacy
private key cryptography
secret keys
attestation
malware
code attestation technique
data encryption
data memory
data repositories
drones
group attestation scheme
malicious physical/cyber attacks
mobile data collectors
privacy-sensitive data
secret key protection
secure communications
software attestation
software integrity
software-based attestation
Table lookup
tampered drones
whitebox cryptography
Resiliency
Human behavior
pubcrawl
composability
biblio
A dynamic search space approach to improving learning on a simulated Flapping Wing Micro Air Vehicle
Submitted by
el_wehby
on Thu, 05/17/2018 - 6:51pm
acquisition time
aerospace components
aerospace simulation
Atmospheric modeling
autonomous aerial vehicles
candidate solution representations
Computational modeling
dynamic search space approach
EA search
Evolutionary algorithms
evolutionary computation
flight behavior
Force
frequency control
FW-MAV
FW-MAV wing gaits
gait analysis
learning
learning (artificial intelligence)
meta-heuristic search support
microrobots
Oscillators
physical damage
restriction/access control methods
search problems
simulated insect-like flapping-wing microair vehicle
Table lookup
wing flapping patterns
1239196
biblio
MUTARCH: Architectural diversity for FPGA device and IP security
Submitted by
grigby1
on Tue, 01/23/2018 - 3:24pm
architectural diversity
automotive systems
biomedical systems
bitstream encryption
collaboration
composability
configuration file
diverse applications
encryption
field programmable gate arrays
FPGA device
Hardware
in-field reconfiguration
intellectual property blocks
Internet of Things
IoT
IP blocks
IP piracy
IP security
logical configuration keys
logic circuits
microprocessor chips
modern remote upgrade techniques
MUTARCH
physical configuration keys
Policy
policy-based governance
pubcrawl
Resiliency
security through diversity principle
static keys
Table lookup
time-varying keys
Transforms
unauthorized in-field reprogramming
biblio
FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption
Submitted by
grigby1
on Thu, 04/20/2017 - 12:40pm
advanced encryption standard (AES)
AES-128
AES-192
AES-256
AES Rijndael algorithm
Algorithm design and analysis
algorithmic functions
Clocks
composability
Cryptography
decryption
encryption
Field Programmable Gate Array (FPGA)
field programmable gate arrays
FPGA based hardware implementation
Galois field multiplications
Galois fields
GF (28)
Hardware Description Language (HDL)
hardware description languages
inverse mix-columns transformations
Inverse S-Box transformations
network on chip
network on chip security
network security algorithm
pre-calculated look-up tables
precalculated LUT
pubcrawl
Resiliency
Rijndael
Scalability
secure data transmission
Table lookup
timing
Verilog-HDL
Virtex-7 XC7VX690T chip
wired digital communication networks
wireless digital communication networks
Xilinx ISE Design Suite-14.7 Tool
Xilinx Virtex-7 FPGA
Xilinx XPower Analyzer
biblio
Hardware-assisted code obfuscation for FPGA soft microprocessors
Submitted by
grigby1
on Mon, 02/27/2017 - 12:53pm
Code Obfuscation
Complexity theory
data dependent control flow modification
encoding
encryption
field programmable gate arrays
FPGA soft microprocessors
Hardware
hardware assisted code obfuscation
hardware-software codesign
many embedded FPGA system
microprocessor chips
minimal hardware overhead
pubcrawl170107
security of data
Soft microprocessor
Software
software confidentiality
software security
Switches
Table lookup
biblio
High-Throughput and Memory-Efficient Multimatch Packet Classification Based on Distributed and Pipelined Hash Tables
Submitted by
BrandonB
on Wed, 05/06/2015 - 11:57am
asynchronous pipeline architecture
bit rate 26.8 Gbit/s to 93.1 Gbit/s
complicated multidimensional search
content-addressable storage
Cryptography
distributed hash tables
edge-grouping
encoding
hash table
hash table lookup
high-throughput multimatch
hybrid perfect hash table construction
IEEE transactions
intermediate data structure
interstage parallel access
Memory management
memory-efficient multimatch
multimatch packet classification problem
network intrusion detection
packet classification
packet-level accounting
pipelined hash tables
Pipelines
Power demand
search engines
security of data
signal classification
signature tree
signature tree structure
single-dimensional searches
steep performance degradation
Table lookup
TCAM
ternary content addressable memory
ternary content addressable memory (TCAM)
Throughput
throughput via
traffic traces
tree data structures
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