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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
application specific integrated circuits
biblio
Design of Boolean Chaotic Oscillator Using CMOS Technology for True Random Number Generation
Submitted by
grigby1
on Thu, 05/24/2018 - 11:16am
45nm CMOS technology
application specific integrated circuits
authentication security
cadence virtuoso
Cadence Virtuoso tool
Capacitors
chaos
CMOS
CMOS Boolean Chaotic Oscillator Design
CMOS integrated circuits
Cryptography
data transmission security
delays
Generators
Human behavior
Inverters
Logic gates
message authentication
Metrics
National Institute of Standards and Technology
NI ELVIS platform
Oscillators
pubcrawl
random cryptographic keys
random key generation
random number generation
random number generators
random numbers
resilience
Resiliency
Ring oscillators
Scalability
security keys
biblio
System architectural design of a hardware engine for moving target IPv6 defense over IEEE 802.3 Ethernet
Submitted by
K_Hooper
on Wed, 02/28/2018 - 10:38am
application specific integrated circuit variant
application specific integrated circuits
ASIC
CISC architecture
Clocks
collaboration
complex instruction set computer architecture
composability
computer network security
cryptographic dynamic addressing
Encapsulation
Engines
federal networks
FPGA
Hardware
hardware engine
HE-MT6D
Homeland Security Cyber Security Division
IEEE 802.3 Ethernet
Instruction sets
internet
IP networks
IPv6
ipv6 security
keyed access
Logic gates
Metrics
moving target defense
moving target IPv6 defense
MT6D processor
network address
network infrastructure
network level
network packet processor
network processor
network time protocol listener
obscuration technique
operating system kernel
operating system kernels
personal area networks
Protocols
pubcrawl
Register Transfer Level network security processor implementation
Resiliency
Routing protocols
RTL development
system architectural design
system level functions
biblio
Implementation and optimization of A5-1 algorithm on coarse-grained reconfigurable cryptographic logic array
Submitted by
grigby1
on Wed, 02/21/2018 - 12:41pm
A5-1
A5-1 algorithm optimization
Algorithm design and analysis
application specific integrated circuits
ASIC
bit rate 162.87 Mbit/s
cellular radio
CGRCA
Ciphers
coarse-grained reconfigurable cryptographic logic array
composability
Conferences
Cryptography
field programmable gate arrays
FPGA
frequency 162.87 MHz
GSM
Metrics
Microelectronic Security
Noise measurement
performance optimization
pubcrawl
real-time requirements
reconfigurable architectures
resilience
Resiliency
resource allocation
resource consumption
resource-based path seeking algorithm
RPS adaptive algorithm
shift registers
stream cipher
telecommunication security
Throughput
voice data encryption
biblio
A novel transition effect ring oscillator based true random number generator for a security SoC
Submitted by
grigby1
on Wed, 02/21/2018 - 12:41pm
Stochastic Computing Security
Altera Cyclone series FPGA platform
application specific integrated circuits
balanced TERO TRNG
CMOS ASIC process
composability
delays
Entropy
entropy source
field programmable gate arrays
FPGA
Inverters
Layout
Metrics
Microelectronic Security
Oscillators
pubcrawl
random number generation
random number generator
resilience
Resiliency
Ring oscillators
security SoC
system-on-chip
transition effect ring oscillator
true random number generator
biblio
Platform agnostic, scalable, and unobtrusive FPGA network processor design of moving target defense over IPv6 (MT6D) over IEEE 802.3 Ethernet
Submitted by
grigby1
on Tue, 01/16/2018 - 5:31pm
application specific integrated circuits
ASIC
complex instruction set computer instruction set architecture
Computers
Cryptography
Electrical Engineering
embedded application-specified integrated circuit
EPON
field programmable gate arrays
FPGA
IEEE 802.3 Ethernet
IEEE 802.3 Standard
Instruction sets
IP networks
IPv6
IPv6 interfaces
Local area networks
low power wireless personal area networks
Metrics
modular crypto engine
moving target defense
moving target defense over IPv6
MT6D
network processor
network-based keyed access
pubcrawl
register transfer level logic
Resiliency
RTL-based Network Time Protocol v4 synchronization
biblio
"Improved serial 2D-DWT processor for advanced encryption standard"
Submitted by
grigby1
on Mon, 02/13/2017 - 12:08pm
advanced encryption standard
AES
application specific integrated circuits
ASIC circuit design
CMOS technology
compression ratio
Cryptography
data compression
discrete wavelet transform
discrete wavelet transforms
DWT
encryption
frequency 333 MHz
Hardware
high speed encryption
Image coding
image data security
lifting scheme algorithm
low power ASIC
pubcrawl170102
Quantization (signal)
RTL-GDSII
secured image processing
serial 2D-DWT processor
serialized DT processor
size 65 nm
biblio
Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm
Submitted by
BrandonB
on Wed, 05/06/2015 - 10:49am
acceptable complexity
Algorithm design and analysis
application specific integrated circuits
Application-specific integrated circuit (ASIC)
ASIC analysis
Circuit faults
computational complexity
concurrency control
Cryptography
error coverage
error detection
Hardware
hardware overhead reduction
hashing
high performance
high-performance concurrent error detection scheme
injection-based fault simulations
integrity checking
Keccak
low-complexity recomputing
parallel processing
performance overheads
pseudorandom number generation
Reliability
robust hardware implementations
rotated operand-based scheme
secure hash algorithm
secure hash algorithm (SHA)-3
security
SHA-3 algorithm
step-forward toward
Transient analysis
biblio
Detection of hardware Trojan in SEA using path delay
Submitted by
BrandonB
on Wed, 05/06/2015 - 10:33am
Algorithm design and analysis
application specific integrated circuits
ASIC design flow
Cryptography
delays
encryption
fabless design house
gate level Trojan insertions
GDSII
GDSII hard macros
Hardware
hardware Trojan detection
Hardware Trojan horses (HTH)
hardware Trojan horses insertion
HTH detection and insertion
invasive software
IP blocks
layout level Trojan insertions
logic circuits
Logic gates
path delay
payload Trojan
payload Trojan detection rate
Scalable Encryption Algorithm (SEA)
scalable encryption algorithm crypto
SEA crypto
Trojan circuits
Trojan horses
