Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
system-on-chip
biblio
A Benchmark Suite of Hardware Trojans for On-Chip Networks
Submitted by
grigby1
on Fri, 05/15/2020 - 12:45pm
network on chip security
Scalability
resilience
Resiliency
Metrics
benchmark suite
Benchmark testing
benchmarks
Cryptography
Functional testing
Hardware
hardware trojan
Hardware Trojans
HT defense methods
Information Leakage
invasive software
manycore systems
multicore systems
multiprocessing systems
network-on-chip
NoC
on-chip networks
performance degradation
Routing
security
side channel analysis
standards
system-on-chip
Trojan horses
biblio
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices
Submitted by
grigby1
on Fri, 05/15/2020 - 12:45pm
network on chip security
Scalability
resilience
Resiliency
Metrics
Artificial Neural Networks
circuit optimisation
Deep Neural Network accelerator
deep neural network inferences
Design Space Exploration
Energy analysis
integrated circuit design
Internet of Things
IoT edge devices
low-power electronics
massive parallel cores
Measurement
Memory management
memory size
network routing
network-on-chip
neural chips
Neurons
NoC-based deep neural network accelerators
On-chip communication
performance evaluation
resource-constrained embedded devices
Space exploration
system-on-chip
biblio
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip
Submitted by
grigby1
on Fri, 05/15/2020 - 12:30pm
pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
bit shuffling mechanism
Buffer storage
computer architecture
cryptographic modules
Cryptography
Degradation
denial of service attack
Hardware
hardware security issues
hardware trojan
Router Architecture
performance evaluation
integrated circuit design
microprocessor chips
MPSoC
multiprocessing systems
multiprocessor system on chips
network-on-chip
NoC
performance degradation Hardware Trojan attacks
run time mitigation
security
semiconductor design
system-on-chip
Trojan horses
biblio
Hardware-Assisted Security in Electronic Control Units: Secure Automotive Communications by Utilizing One-Time-Programmable Network on Chip and Firewalls
Submitted by
grigby1
on Fri, 05/15/2020 - 12:30pm
pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
advanced driver assistance systems
authentication
automotive communications
automotive controller area network-bus communications
automotive electronics
Automotive engineering
controller area networks
cyber-enabled automotive system
data privacy
driver information systems
electronic control units
enjoyable driving
firewalls
Firewalls (computing)
Hardware
hardware firewalling
hardware-assisted security
network-on-chip
off-chip networking techniques
on-chip network physical isolation
one-time-programmable network
Secure Automotive Communications
secure execution environments
smart automotive technologies
software-dominated enhancements
system-level countermeasures
system-on-chip
system-wide cryptographic techniques
threat models
Trusted Electronic Control Units
vehicle-to-vehicle communications
biblio
Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs
Submitted by
grigby1
on Fri, 05/15/2020 - 12:30pm
pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
attack efficiency
cache activity
cache line
cache location
cache memories
cache storage
computer architecture
Cryptography
earthquake attack
Earthquakes
encryption
Glass
microprocessor chips
MPSoC configurations
MPSoC Glass
multiprocessing systems
network-on-chip
Network-on-Chip communication structure
NoC
on-chip connectivity
optimized differential cache-collision attacks
optimized variant
programming flexibility
security concerns
Security NoC
system-on-chip
Systems-on-Chips
timing
Timing attack
timing measurements
Timing Side-channel Attack
biblio
Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service Attacks
Submitted by
aekwall
on Mon, 05/11/2020 - 11:09am
Scalability
telecommunication security
learning (artificial intelligence)
Resiliency
pubcrawl
wireless sensor networks
Wireless communication
Metrics
machine learning
telecommunication network routing
telecommunication computing
radio networks
system-on-chip
DoS
Hardware Security
error correction codes
radiofrequency interference
DoS attack
Jamming
denial-of-service attack
machine learning classifier
HT
network-on-chip
data transfer security threats
denial-of-service attacks
internal hardware Trojans
jamming attack
low-power transceivers
ML classifiers
network-on-chip communications
NoC switches
nonscalable multihop data transmission paths
On chip interconnect
On chip security
on-chip data transfer
on-chip wireless medium
persistent jamming attack
radio transceivers
radiofrequency interconnections
random burst error correction code
Switches
switching networks
WiNoC security
wired NoC architectures
wireless interconnection
Wireless NoC
wireless NoC architectures
network on chip security
biblio
Security Network On-Chip for Mitigating Side-Channel Attacks
Submitted by
aekwall
on Mon, 05/11/2020 - 11:08am
security of data
Scalability
learning (artificial intelligence)
Resiliency
pubcrawl
Metrics
machine learning
physical interaction
system-on-chip
system security
sensors
Attack detection
timing
Hardware Security
side-channel attacks
integrated circuit design
data analysis
malicious activity
integrated circuits
network-on-chip
active attack
advance invasive attacks
advance noninvasive attacks
advanced technology nodes
attack-specific countermeasures
compromised device
contemporary hardware threats
design complexity
electromagnetic analysis attacks
electromagnetic interference
hardware security threats
high-confidence security network on-chip
individual threats
machine learning security IC
malicious physical interference
modern ICs
multiple countermeasures
on-chip distribution networks
On-chip power delivery
on-chip voltage variations
operating device-under-attack
robust confidence security network on-chip
security networks
Side-channel attack
side-channel attack mitigation
strict performance requirements
trained ML ICs
network on chip security
biblio
Alternatives to Fault Injections for Early Safety/Security Evaluations
Submitted by
aekwall
on Mon, 03/09/2020 - 11:17am
Safety
security of data
Scalability
Hardware
Software
embedded systems
SoC
system-on-chip
Time measurement
Resiliency
pubcrawl
Metrics
Reliability
cost reduction
ISO standards
safety-critical software
Human Factors
CPS
Circuit faults
hardware-software codesign
cyber physical systems
dependability analysis
fault injections
functional safety standards
HW-SW systems
intertwined hardware
ISO 26262
market pressure
radiation testing
RTL fault injection campaigns
system dependability constraints
Security Risk Estimation
biblio
Restricting Switching Activity Using Logic Locking to Improve Power Analysis-Based Trojan Detection
Submitted by
grigby1
on Wed, 02/26/2020 - 4:38pm
circuit block extraction
circuit power
cyber physical systems
design for hardware trust
fabrication foundries
gate level
Hardware
Hardware Security
hardware Trojan detection
hardware Trojan threat
HT activity
HT power
HT-infected circuits
industrial property
integrated circuit layout
intellectual properties
invasive software
IP piracy
IPS
Logic gates
logic locking
logic locking method
malicious circuits
million-gate circuits
outsourcing
PCA-based HT detection methods
power analysis-based Trojan detection
power consumption
power consumption analysis
Power demand
principal component analysis
Process Variations
pubcrawl
resilience
Resiliency
security
semiconductor companies
small sub-circuit collection
supply chain security
Switches
system-on-chip
trojan horse detection
Trojan horses
untrustworthy fabs
biblio
FIXER: Flow Integrity Extensions for Embedded RISC-V
Submitted by
aekwall
on Mon, 02/24/2020 - 11:01am
security of data
Scalability
Internet of Things
data integrity
Hardware
security
embedded systems
reduced instruction set computing
system-on-chip
computer architecture
Buffer overflows
Resiliency
pubcrawl
composability
software reusability
Software Architecture
Bars
Human Factors
code reuse attacks
ROP
return oriented programming
program compilers
security framework
RISC-V
buffer overflow
Code injection
coprocessors
fine-grained control-flow integrity
FIXER
flow integrity extensions for embedded RISC-V
integrated Rocket Custom Coprocessor
low-power embedded devices
open source architecture
RISC-V architecture
RISC-V processor core
RISC-V SoC platform
RISC-V toolchains
Rockets
security extension
shadow stack
1
2
3
4
5
6
next ›
last »
