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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
system-on-chip
biblio
On-chip Data Security Against Untrustworthy Software and Hardware IPs in Embedded Systems
Submitted by
aekwall
on Wed, 05/01/2019 - 12:42pm
3PIP
composability
Cryptography
dual-core ARM processor
embedded systems
field programmable gate arrays
FPGA-based embedded systems
golden reference model
Hardware
hierarchical top-down structure
implementation
Intel DE1-SoC board
IP networks
low-latency hardware
memory access
memory protection design
memory protection unit
memory security
Metrics
microprocessor chips
on-chip memory blocks
pubcrawl
reconfigurable logic fabric
Resiliency
security
security of data
security services
SoC FPGA
software IP
static detection methods
system-on-chip
third-party IP cores
third-party IPs
biblio
LiteHAX: Lightweight Hardware-Assisted Attestation of Program Execution
Submitted by
aekwall
on Wed, 02/13/2019 - 11:58am
attestation
composability
control-flow attacks
control-flow attestation schemes
data flow computing
data integrity
data-flow events
data-oriented programming
DOP attacks
embedded Internet of Things devices
embedded systems
hardware-assisted remote attestation scheme
Human behavior
Internet of Things
lightweight hardware-assisted attestation of program execution
LiteHAX
malicious modification
malware
Program processors
programming
pubcrawl
RA
reduced instruction set computing
remote device integrity
Resiliency
RISC-based embedded devices
RISC-V system-on-chip
Runtime
runtime attestation
security
security of data
security service
SoC
software binaries
system-on-chip
Trusted Computing
biblio
Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm
Submitted by
grigby1
on Wed, 09/12/2018 - 11:25am
resilience
network security
FPGA
high level synthesis
pubcrawl
Resiliency
Scalability
high-level synthesis
system monitoring
Hardware
Payloads
Algorithm design and analysis
computer network security
real-time systems
Program processors
search problems
parallel processing
system-on-chip
Zynq
TCP
Inspection
deep packet inspection
Accelerator
BM string search algorithm
Boyer-Moore
Boyer-Moore algorithm
High-Le'vel Synthesis
MISD parallelism
Network Monitoring
Platform Based Design
platform based design methodologies
Programmable SoC
real-time on-line pattern search
SIMD
string matching
SystemC
TCP packets
Xilinx Zynq programmable SoC
biblio
High confinement and low loss Si3N4waveguides for miniaturizing optical coherence tomography
Submitted by
grigby1
on Thu, 08/23/2018 - 11:59am
privacy
cyber-physical systems
pubcrawl
Resiliency
composability
resilience
Imaging
system-on-chip
Integrated optics
optical losses
high confinement thermally tunable silicon nitride waveguide
low loss silicon nitride waveguide
optical coherence tomography
Optical interferometry
optical tomography
optical tuning
Optical waveguides
Optimized production technology
Propagation losses
Si3N4
Silicon compounds
size 42.0 cm
confinement
biblio
Smart bluetooth low energy security system
Submitted by
grigby1
on Thu, 08/23/2018 - 11:35am
BLE (Bluetooth Low Energy)
biometric
BLE technology
Bluetooth
bluetooth security
building management systems
Cameras
composability
Conferences
energy consumption
energy security
Human behavior
human factor
image transmission
IoT (Internet of Things)
low energy consumption security system
physical lock
PSoC 4 BLE
pubcrawl
resilience
Resiliency
security
sensors
Servomotors
smart Bluetooth low energy security system
smart phones
smartphone
surveillance system
system-on-chip
Web page
Web site
wireless connection
wireless technologies
biblio
Minimum energy quantized neural networks
Submitted by
grigby1
on Mon, 06/11/2018 - 3:24pm
pubcrawl
Resiliency
Scalability
Hardware
neural nets
energy consumption
telecommunication security
Neural networks
Training
deep learning
resilience
Memory management
Metrics
Random access memory
system-on-chip
energy conservation
power aware computing
Mobile communication
approximate computing
arbitrary fixed point precision
automated minimum-energy optimization
BinaryNets
complex arithmetic
fixed point arithmetic
fundamental trade-off
generic hardware platform
higher precision operators
int4 implementations
int8 networks
iso-accuracy depending
low precision weights
Minimum Energy
minimum energy QNN
QNN training
Quantized Neural Network
quantized neural networks
wider network architectures
network on chip security
biblio
Study of secure boot with a FPGA-based IoT device
Submitted by
grigby1
on Mon, 06/11/2018 - 3:23pm
pubcrawl
Resiliency
Scalability
Internet of Things
Cryptography
encryption
authentication
Trojan horses
field programmable gate arrays
system security
resilience
Metrics
Decoding
system-on-chip
bitstream decoding
critical components
effective security provisioning
encrypt system boot image
FPGA bitstream
FPGA design
FPGA-based IoT device
host processor computation power
infrastructure components
IoT system
Secure Boot
software-based security implementation
Trojan Horse attacks
Xilinx Zynq-7000 Series System-on-Chip ZC706 prototype board
network on chip security
biblio
PUFSec: Protecting physical unclonable functions using hardware isolation-based system security techniques
Submitted by
grigby1
on Mon, 06/11/2018 - 3:20pm
Access Control
ARM Processor
composability
computer architecture
computer network security
control systems
Data protection
Denial of Service attacks
DoS attacks
Hardware
hardware isolation
internal PUF design
Metrics
Modeling Attacks
Monitoring
Networked Control Systems Security
physical unclonable function protection
pubcrawl
PUF hardware
PUF workflow
PUFSec framework
resilience
Resiliency
secure architecture extension
security challenges
security compromises
security policies
security protection
Software
system security techniques
system-on-chip
Xilinx SoC
biblio
14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with \#x003E;0.1 timing error rate tolerance for IoT applications
Submitted by
grigby1
on Thu, 06/07/2018 - 3:07pm
1.2GHz 568nJ/prediction sparse deep-neural-network engine
28nm SoC
aggregate timing violation rates
algorithmic error tolerance
algorithmic resilience
circuit resilience
circuit-level timing violation tolerance
data sparsity
datapath logic
Energy Efficiency
Engines
Error analysis
FCLK scaling
frequency 1 GHz
frequency 1.2 GHz
frequency 667 MHz
Internet of Things
IoT applications
neural nets
Neural Network Resilience
Program processors
programmable FC-DNN accelerator design
pubcrawl
Razor timing violation detection
resilience
Resiliency
sign-magnitude number format
system-on-chip
Throughput
timing
timing error rate tolerance
VDD scaling
biblio
Scalable stochastic-computing accelerator for convolutional neural networks
Submitted by
grigby1
on Thu, 06/07/2018 - 3:06pm
arrays
Biological neural networks
computational complexity
ConvNets
convolution
convolutional neural network
convolutional neural networks
neural nets
Neural Network Resilience
pubcrawl
Recognition accuracy
resilience
Resiliency
SC-based neural networks
scalable stochastic-computing accelerator
Stochastic computing
system-on-chip
Weight parameter retraining
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