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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
system-on-chip
biblio
DVFS as a Security Failure of TrustZone-enabled Heterogeneous SoC
Submitted by grigby1 on Tue, 11/17/2020 - 1:39pm
security
IP networks
Trusted Computing
pubcrawl
Metrics
Resiliency
embedded systems
composability
computer architecture
Instruction sets
hardware trojan
Receivers
resilience
energy consumption
operating systems (computers)
operating systems
operating system
electronic engineering computing
power aware computing
Clocks
system-on-chip
Frequency modulation
ARM TrustZone
AXI bus
DVFS
Dynamic Voltage and Frequency Scaling
embedded system security
frequency regulator
nonsecure ARM core
Regulators
secure ARM core
security failure
TrustZone-enabled heterogeneous SoC
TrustZone-enabled System-on-Chip
voltage regulator
Operating systems security
biblio
Customized Locking of IP Blocks on a Multi-Million-Gate SoC
Submitted by aekwall on Mon, 11/09/2020 - 12:31pm
IP networks
Hardware
security
system-on-chip
Resiliency
pubcrawl
composability
policy-based governance
logic locking
integrated circuits
Logic gates
industrial property
integrated circuit design
Erbium
logic design
IP piracy
industrial designs
integrated circuit manufacture
IP block
multimillion-gate SoC
multiple IP blocks
off-site untrusted fabrication facilities
Solid modeling
VLSI testing
biblio
Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints
Submitted by grigby1 on Mon, 11/02/2020 - 12:36pm
composability
delays
graph theory
Hardware
hardware trojan
industrial property
intellectual property security
IP networks
logic design
malicious inclusions
MPSoC
multiprocessing systems
Multiprocessor System-on-Chips
performance constraints
policy-based governance
Processor scheduling
pubcrawl
resilience
Resiliency
schedule length
Schedules
scheduling
security
security of data
security-driven task scheduling
system level security constraints
System performance
system-on-chip
Task Analysis
task scheduling
Trojan horses
two-stage performance-constrained task scheduling algorithm
biblio
Robust Digital Signature to Protect IP Core against Fraudulent Ownership and Cloning
Submitted by grigby1 on Mon, 11/02/2020 - 11:30am
composability
consumer electronic devices
crypto digital signature approach
Cryptography
digital signal processing chips
digital signature
digital signature processing cores
digital signatures
DSP
encoding
encryption
fraudulent ownership
industrial property
intellectual property security
IP cloning
IP core
multimedia based reusable Intellectual property cores
multiple security modules
policy-based governance
Protection.
pubcrawl
resilience
Resiliency
robust digital signature
synthesis
system-on-chip
system-on-chips
watermarking approach
biblio
SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection
Submitted by grigby1 on Mon, 11/02/2020 - 11:29am
composability
dynamic intrusion detection approach
field programmable gate arrays
FPGA platform
Hardware
Hardware Security
hardware tracing
Hardware Trojans
industrial property
intellectual properties
intellectual property security
Intrusion Detection
IP networks
Monitoring
open source processor
policy-based governance
pubcrawl
Registers
resilience
Resiliency
Runtime system
security
SoCINT
SoCs
software tools
system-on-chip
Trojan horses
biblio
FPGA Bitstream Security: A Day in the Life
Submitted by grigby1 on Mon, 11/02/2020 - 11:29am
bitstream file
bitstream lifecycle
Bitstream Protection
composability
encryption
field programmable gate arrays
FPGA bitstream security
FPGA designs
FPGA security
industrial property
intellectual properties
intellectual property security
IPS
policy-based governance
pubcrawl
reconfigurable architectures
resilience
Resiliency
security
security concerns
SoC platform
system integrator
system-on-chip
system-on-chip platforms
biblio
A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation
Submitted by grigby1 on Mon, 11/02/2020 - 11:28am
authorisation
Clocks
Complexity theory
composability
controlled scan chain isolation
data integrity
Data Integrity Attacks
data manipulation
data protection scheme
data sniffing
debug
design for test
Diagnosis
electronic design automation
embedded instruments
embedded systems
graph coloring problem
graph colouring
graph theory approach
hidden test-data registers
IEEE standards
IEEE Std 1687
IEEE Std. 1687
IJTAG
IJTAG network
IJTAG security
Instruments
intellectual property security
isolation signals
microprocessor chips
on-chip access
on-chip instruments
policy-based governance
power consumption
pubcrawl
Registers
resilience
Resiliency
scan chain
security
security of data
system-on-chip
system-on-chip designs
third party intellectual property providers
unauthorized user access
untrusted sources
biblio
A Trusted Bluetooth Performance Evaluation Model for Brain Computer Interfaces
Submitted by grigby1 on Fri, 09/04/2020 - 3:27pm
security
data privacy
privacy
mobile computing
pubcrawl
composability
Resiliency
resilience
Human behavior
cyber physical systems
feedback
Bluetooth
ambulatory care
BCI hardware performance
BCI Safety
Bluetooth operating parameters
brain computer interface
brain computer interfaces
brain function classification accuracy
brain state
brain-computer interfaces
Cyber Physical System
electroencephalography
fitness tracking
medical signal processing
mobile BCI technology
Mobile Cyber Security
mobile EEG-based BCI applications
mobile neurofeedback applications
neurophysiology
Performance Rating
system-on-chip
telemedicine
TMBCI
Trusted Mobile BCI Performance
Wearable
bluetooth security
biblio
Machine Learning Bluetooth Profile Operation Verification via Monitoring the Transmission Pattern
Submitted by grigby1 on Fri, 09/04/2020 - 3:27pm
security
telecommunication security
pubcrawl
composability
Resiliency
resilience
Human behavior
machine learning
feature extraction
classifier
learning (artificial intelligence)
cyber physical systems
formal verification
Decision Tree
system-on-chip
telecommunication computing
Bluetooth
Blue-tooth
Bluetooth profile operation verification
Bluetooth SoC
Bluetooth System-on-Chip
communication complexity
custom low-frequency integrated circuit
electronic engineering computing
Hardware Security
hardware-software security
integrated circuit manufacture
k-nearest neighbor
license communication IC
low computational complexity
low-cost legacy technology
mobile radio
profile classification algorithm
radio frequency output power
RF envelope detector
RF output power
RF Power
signal classification
smart descriptive time-domain feature extraction
Supervisory Circuit
support vector machine
transmission pattern
Cyber Physical System
bluetooth security
biblio
Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs
Submitted by grigby1 on Fri, 07/03/2020 - 12:26pm
computer architecture
CPU-DMA based architecture
deep packet inspection
ESL
field programmable gate arrays
Hardware
hardware accelerators
hardware-IP based architecture
hybrid CPU/FPGA
Inspection
logic design
Mentor Vista
pubcrawl
resilience
Resiliency
Scalability
search engines
Software
system on chip
system-on-chip
system-on-chip FPGA
time-domain analysis
time-varying systems
TLM
transaction level modeling
virtual platform
virtual platforms
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