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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
system-on-chip
biblio
Multi-core Heterogeneous Video Processing System Design
Submitted by
aekwall
on Mon, 02/10/2020 - 10:58am
field programmable gate arrays
IP networks
Scalability
system-on-chip
Resiliency
pubcrawl
Metrics
video signal processing
microprocessor chips
multiprocessing systems
hardware acceleration
image binarization
image processing speed
multi-core heterogeneous
multicore heterogeneous acceleration processing
multicore heterogeneous computing technology
multicore heterogeneous video processing system design
otsu adaptive binarization
Otsu binarized hardware-accelerated IP
real-time video image processing system
Xilinx Zynq platform
Zynq
multicore computing security
biblio
Run-time Detection and Mitigation of Power-Noise Viruses
Submitted by
aekwall
on Mon, 02/10/2020 - 10:58am
security
Scalability
power aware computing
Resiliency
pubcrawl
Metrics
regression analysis
microcontrollers
system-on-chip
computer viruses
Benchmark testing
Microprocessors
multiprocessing systems
Resonant frequency
Arm multicore processor
data corruptions
multicore microprocessors
operating frequency
power viruses
power-noise attacks
power-noise virus detection
power-noise virus mitigation
resonance detection
run-time estimation
run-time system
system crashes
Threshold voltage
Viruses (medical)
voltage emergencies
voltage noise data
multicore computing security
biblio
Heterogenic Multi-Core System on Chip for Virtual Based Security
Submitted by
aekwall
on Mon, 02/10/2020 - 10:58am
Scalability
Cryptography
encryption
Hardware
system-on-chip
Kernel
Resiliency
pubcrawl
Metrics
standards
neural nets
Decoding
microsoft windows
Computers
assembly language
Image Processing
multiprocessing systems
DES
signal processing
AES
virtual reality
Cipher
coding information
GOST
heterogenic multi-core system-on-chip
heterogenic multicore system on chip
neural network emulation
neuromatrix
standard symmetric key block cipher
the GOST
virtual-based security
multicore computing security
biblio
A Security Architecture for RISC-V based IoT Devices
Submitted by
aekwall
on Mon, 02/10/2020 - 10:43am
IoT
Monitoring
Internet of Things
Hardware
IoT applications
Software
reduced instruction set computing
system-on-chip
embedded devices
Resiliency
pubcrawl
composability
Cryptography
automation
small and medium-sized enterprises
small-to-medium enterprises
security architecture
Predictive Metrics
3D-SiP
authenticated watchdog timer
core security features
customizable Internet of Things platform
Device Security
Fraunhofer Institutes
IoT market
medium security level
p
RISC-V
RISC-V based IoT devices
RISC-V ISA
scalable computing subsystem
Secure Boot
secure deployment
security concept
SIP
SME
strict power constraints
system-in-package
three dimensional system-in-package
Universal Sensor Platform SoC
USeP SoC
watchdog timer
Microelectronics Security
biblio
On Integrating Lightweight Encryption in Reconfigurable Scan Networks
Submitted by
aekwall
on Mon, 01/20/2020 - 11:01am
-play instrument wrapper
appropriate counter-measures
Ciphers
Cryptographic Protocols
Cryptography
data integrity
data privacy
debug modules
embedded instrumentation
embedded systems
encryption
field programmable gate arrays
flexible access
FPGA-based implementation
Hardware
Hardware Security
IEEE standards
IEEE Std 1687
IEEE Std 1687 RSNs
IJTAG
industrial property
instrument wrapper
Instruments
integrated circuit testing
integrating lightweight encryption
intellectual property
Lightweight Ciphers
lightweight stream cipher
logic testing
maintenance
malicious users
novel hardware
on-chip instrumentation
pubcrawl
PUF
reconfigurable scan networks
Resiliency
RSN
Scalability
seamless integration
secret keys
Secure Wrapper
self-test
sensitive data
Software
software combined approach
system-on-chip
testing workflow
versatile software toolchain
biblio
Timing Analysis for Diffie Hellman Key Exchange In U-BOOT Using Raspberry Pi
Submitted by
grigby1
on Mon, 12/30/2019 - 1:18pm
cryptographic
cryptographic era
Cryptographic Protocols
Cryptography
DHKE protocol
diffie hellman key exchange
Diffie Hellman Key Exchange protocol
Discrete Log Hard Problem
embedded device
embedded systems
exponentiation
firmware
Force
GMP bignum library
Metals
modular exponentiation
networked embedded systems security
Protocols
pubcrawl
public key cryptography
Raspberry Pi
Raspberry-pi
Resiliency
Scalability
Secret key
security schemes
side channel attack
system-on-chip
telecommunication security
timing
Timing attack
timing attacks
timing patterns
tools
U-Boot bare metal
unsecure communication channel
word length 2048.0 bit
word length 64.0 bit
biblio
Formal Security Verification of Concurrent Firmware in SoCs Using Instruction-Level Abstraction for Hardware*
Submitted by
grigby1
on Tue, 12/17/2019 - 11:21am
security of data
resilience
pubcrawl
Metrics
Resiliency
composability
Hardware
microprocessor chips
Frequency modulation
Access Control
cyber-physical systems
cognition
cyber-physical system
program verification
firmware
Microprogramming
system-on-chip
concurrency (computers)
Concurrency
multi-threading
architecture level
bit-precise reasoning
concurrent firmware
firmware-visible behavior
formal security verification
Instruction-Level Abstraction
intellectual property blocks
multithreaded program verification problem
Secure Boot design
SoC security verification
software verification techniques
Systems-on-Chip
Predictive Metrics
biblio
Routing Aware and Runtime Detection for Infected Network-on-Chip Routers
Submitted by
grigby1
on Mon, 11/04/2019 - 11:39am
Hardware
hardware trojan
integrated circuits
invasive software
logic design
malicious Hardware Trojans
Malicious-tolerant Routing Algorithm
Metrics
MPSoC
multiprocessing systems
Multiprocessors System-on-Chip
network routing
network-on-chip
network-on-chip architecture
NoC
outsourcing
pubcrawl
resilience
Resiliency
Router Systems Security
Routing
Runtime
runtime detection
secret key leaking
secure routing algorithm
security
security attacks
System recovery
system-on-chip
Trojan horses
biblio
ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies
Submitted by
aekwall
on Tue, 10/22/2019 - 8:54am
security of data
Monitoring
IP networks
system-on-chip
pubcrawl
policy-based governance
Cryptography
tools
security architecture
Complexity theory
Engines
security policy
formal verification
alternative architecture
artifact
CAD
CAD flow
centralized infrastructure IP
complex steps
critical steps
efficient formal verification
expensive steps
flexible infrastructure IP
functional design flow
illustrative policies
industrial SoC
integrated circuit design
modern SoC design validation
off-the-shelf formal tools
Security Engine
security policy implementation
simulation-based security verification
SoC Security
SoC security policies
SoC Verification
streamlined verification
system-level security policies
verification time
verification tools
Security Policies Analysis
biblio
An Improved Cross-Coupled NAND Gates PUF for Bank IC Card
Submitted by
grigby1
on Wed, 09/11/2019 - 1:45pm
composability
FPGA
Metrics
Microelectronics Security
physical unclonable functions
pubcrawl
resilience
Resiliency
system-on-chip
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