Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
low-power electronics
biblio
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores
Submitted by
aekwall
on Mon, 12/02/2019 - 11:07am
Scalability
Resiliency
pubcrawl
Metrics
Transient analysis
delays
fault tolerance
Fault tolerant systems
Compositionality
program compilers
battery operated low power
battery operated low power high performance devices
circuit optimisation
compiler driven transformation
contradictory design goal optimization
digital signal processing chips
DSP core
electronic device realibility
fault security
Finite impulse response filters
high performance devices
integrated circuit layout
integrated circuit reliability
low-power electronics
optimized low cost transient fault tolerant DSP core
optimized transient fault tolerant DSP
simulated annealing
simulated annealing based floorplan
simulated annealing based optimization process
sub-nanometer technology scale
technology scaling
Transient fault
transient fault tolerant approach
compiler security
biblio
Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications
Submitted by
grigby1
on Mon, 06/11/2018 - 2:48pm
activity factor
average power dissipation
clock cycle
combinatorial logic
composability
cryptographic algorithms
Cryptography
delays
deterministic power
Digital circuits
DPMUX symmetric-logic
dynamic switching energy
Hardware implementations
Information Leakage
linear relationship
logic circuits
logic design
Logic gates
low voltage applications
low-power electronics
Metrics
Microelectronics Security
PAA
power analysis attacks
power consumption
Power dissipation
private key cryptography
probability
Probability distribution
processed data
pubcrawl
resilience
Resiliency
secret cryptographic keys
secured dual-rail-precharge mux
side channel attack
Signal to noise ratio
Switches
biblio
SRAM voltage scaling for energy-efficient convolutional neural networks
Submitted by
grigby1
on Thu, 06/07/2018 - 2:06pm
approximate SRAM
bit error injection
Bit error rate
CMOS memory circuits
ConvNet training
convolutional neural networks
deep learning
electronic engineering computing
elemental semiconductors
energy conservation
energy-efficient convolutional neural network
energy-quality tradeoff
error resiliency
floating-point classification accuracy
Hardware
Hardware Implementation
IoE platform
learning (artificial intelligence)
low-power electronics
low-power embedded system
memory power intensive
memory size 8 KByte
Micromechanical devices
neural nets
Neural Network Resilience
pubcrawl
Random access memory
resilience
Resiliency
Si
Silicon
silicon-on-insulator
size 28 nm
SRAM chips
SRAM voltage scaling
Training
UTBB FD-SOI CMOS
voltage 310 mV
biblio
A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption
Submitted by
grigby1
on Wed, 05/16/2018 - 12:47pm
ARM Cortex A9 processor
Barreto-Naehrig curves
circuit optimisation
Clocks
composability
cryptographic services
cryptographic system
Cryptography
Differential Power Analysis
ECC
embedded
embedded electronic devices
energy consumption
field programmable gate arrays
Hardware
hardware-software co-design
hardware-software codesign
Human behavior
human factor
light-weight hardware/software co-design
lightweight devices
low-power electronics
Metrics
Montgomery multiplier
multiplying circuits
open-source software PBC implementation
optimal Ate pairing
Pairing based cryptography
pairing-based cryptography
PKC
Power measurement
pubcrawl
public key cryptography
public-key cryptography
Repudiation
resilience
Resiliency
sensors
simple power analysis
Software
system-on-chip
Zynq-7020 SoC
biblio
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Submitted by
grigby1
on Wed, 02/21/2018 - 12:38pm
approximate computing
CNN
compute-intensive data processing
computer architecture
computerised instrumentation
Cryptography
data analysis
Data Security
deep convolutional neural network
electroencephalogram
encrypted data collection
encryption
energy 3.16 pJ
energy conservation
Engines
equivalent reduced instruction set computer operation
Face detection
feature extraction
Fulmine tight power envelope
Internet of Things
Internet-of-Things endpoint
IoT endpoint system-on-chip
low-power electronics
Metrics
Multicore Computing
multicore computing security
near-sensor data analytics pipeline
Neural networks
parallel architectures
pubcrawl
regular computing task
remote recognition
resilience
Resiliency
Scalability
secure autonomous aerial surveillance
security of data
seizure detection
sensitive data protection
sensors
size 65 nm
SoC
software programmability
system-on-chip
tightly-coupled multicore cluster
voltage 0.8 V
biblio
Trends on EDA for low power
Submitted by
grigby1
on Wed, 03/08/2017 - 12:54pm
AD 2012
AD 2013
Algorithm design and analysis
Algorithms
cell library
continuous gate sizing
discrete gate sizing
EDA
EDA algorithms
electronic design automation
integrated circuit layout
ISPD Contest
Layout
layout design automation tool
Libraries
Logic gates
Low power
low-power electronics
microprocessor chips
optimization
Physical design
power consumption
Power demand
power optimization
pubcrawl170110
state-of-the-art microprocessors
transistor circuits
transistor layout
transistor network
transistor sizing
Transistors
visualization
visualization tools
