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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
network-on-chip
biblio
Mitigation of Tampering Attacks for MR-Based Thermal Sensing in Optical NoCs
Submitted by aekwall on Thu, 09/30/2021 - 11:43am
Resiliency
Very large scale integration
Trojan horses
trojan
Thermal sensors
thermal sensing
tampering attack
security
Scalability
Handheld computers
pubcrawl
Optical sensors
network-on-chip
network on chip security
micro-ring resonator
Metrics
Hardware Security
biblio
A Secure Network Interface for on-Chip Systems
Submitted by aekwall on Thu, 09/30/2021 - 11:42am
lED
network on chip security
VHDL
Network interfaces
network interface
Multicore processing
Hardware Implementation
decryption
network-on-chip
light emitting diodes
security
Ciphers
AES
Resiliency
Metrics
Scalability
pubcrawl
encryption
tools
computer architecture
biblio
Securing Network-on-Chip Using Incremental Cryptography
Submitted by aekwall on Thu, 09/30/2021 - 11:41am
pubcrawl
encryption
computer architecture
system-on-chip
security
IP networks
network on chip security
network-on-chip
Ciphers
Resiliency
Metrics
Scalability
biblio
A novel Network-on-Chip security algorithm for tolerating Byzantine faults
Submitted by aekwall on Thu, 09/30/2021 - 11:41am
Resiliency
Metrics
Scalability
pubcrawl
Peer-to-peer computing
Cloud Computing
Routing
Circuit faults
computer architecture
wireless sensor networks
network on chip security
NoC
network-on-chip
byzantine faults
BFT
biblio
A Benchmark Suite of Hardware Trojans for On-Chip Networks
Submitted by grigby1 on Fri, 05/15/2020 - 12:45pm
Information Leakage
Trojan horses
system-on-chip
standards
side channel analysis
security
Routing
performance degradation
on-chip networks
NoC
network-on-chip
multiprocessing systems
multicore systems
manycore systems
invasive software
network on chip security
HT defense methods
Hardware Trojans
hardware trojan
Hardware
Functional testing
Cryptography
benchmarks
Benchmark testing
benchmark suite
Metrics
Resiliency
resilience
Scalability
biblio
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices
Submitted by grigby1 on Fri, 05/15/2020 - 12:45pm
low-power electronics
system-on-chip
Space exploration
resource-constrained embedded devices
performance evaluation
On-chip communication
NoC-based deep neural network accelerators
Neurons
neural chips
network-on-chip
network routing
memory size
Memory management
Measurement
massive parallel cores
network on chip security
IoT edge devices
Internet of Things
integrated circuit design
Energy analysis
Design Space Exploration
deep neural network inferences
Deep Neural Network accelerator
circuit optimisation
Artificial Neural Networks
Metrics
Resiliency
resilience
Scalability
biblio
Detecting and Mitigating Low-and-Slow DoS Attacks in NoC-based MPSoCs
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
low-and-slow DoS attack
NoC-based MPSoC architectures
NoC-based MPSoC
NoC
network-on-chip
Network on Chip (NoC)
network attack
Muti-Processor System on Chip (MPSoC)
multisource attacks
MultiProcessor Systems-on-Chip
multiprocessing systems
network on chip security
Internet of Things
internet
Distributed Monitoring
denial-of-service attacks
Denial of Service (DoS) Attack
computer network security
Metrics
Resiliency
resilience
Scalability
biblio
An Adaptive Routing Scheme Based on Q-learning and Real-time Traffic Monitoring for Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
Monitoring
traffic monitoring
traffic load congestion
telecommunication traffic
Routing
real-time systems
real-time
q-learning
Prediction algorithms
performance optimization
packet transmission
optimisation
NoC
network-on-chip
network routing
network congestion
network on chip security
monitor
learning (artificial intelligence)
Heuristic algorithms
DyXY routing
dynamical routing schemes
dynamical routing
dynamical Q-learning routing approach
computer architecture
C-XY routing
adaptive routing scheme
Metrics
Resiliency
resilience
Scalability
biblio
A hierarchical approach to self-test, fault-tolerance and routing security in a Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
packet-switching
local self-test manager
malformed packets
malicious denial-of-service attack
malicious external agent
microprocessor chips
multiprocessing systems
network bandwidth
network-on-chip
NoC
on-chip networks
packet switching
local router
power virus
routing agent
routing security
security concerns
sorting-based algorithm
telecommunication network routing
test algorithms
two-tier approach
two-tier solution
virtual channel flow control
virtual channels
deadlock-free properties
Scalability
resilience
Resiliency
Metrics
associated physical channels
bus interconnects
chip multiprocessors
communication efficiency
computer network reliability
computer network security
deadlock situation
network on chip security
denial-of-service attacks
external source
fault data
fault tolerant computing
fault-information
fault-tolerance aspects
fault-tolerant routing
flit-switching
hierarchical approach
internet
local processing element
biblio
Test methodology for detecting short-channel faults in network on- chip networks using IOT
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
integrated circuit reliability
short-channel fault detection
Routing
routers networks
Power demand
NoC
network-on-chip analysis machine
network-on-chip
network routing
network on- chip networks
network on chip
Monitoring
IoT
Internet of Things
interconnection networks
integrated circuit testing
network on chip security
Integrated circuit interconnections
fault diagnosis
Encoders/decoders
Data Security
Data protection
data encryption
Cryptography
Conferences
computing-intensive data processing
computer architecture
Aerospace electronics
Metrics
Resiliency
resilience
Scalability
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