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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
network-on-chip
biblio
A Benchmark Suite of Hardware Trojans for On-Chip Networks
Submitted by grigby1 on Fri, 05/15/2020 - 12:45pm
network on chip security
Scalability
resilience
Resiliency
Metrics
benchmark suite
Benchmark testing
benchmarks
Cryptography
Functional testing
Hardware
hardware trojan
Hardware Trojans
HT defense methods
Information Leakage
invasive software
manycore systems
multicore systems
multiprocessing systems
network-on-chip
NoC
on-chip networks
performance degradation
Routing
security
side channel analysis
standards
system-on-chip
Trojan horses
biblio
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices
Submitted by grigby1 on Fri, 05/15/2020 - 12:45pm
network on chip security
Scalability
resilience
Resiliency
Metrics
Artificial Neural Networks
circuit optimisation
Deep Neural Network accelerator
deep neural network inferences
Design Space Exploration
Energy analysis
integrated circuit design
Internet of Things
IoT edge devices
low-power electronics
massive parallel cores
Measurement
Memory management
memory size
network routing
network-on-chip
neural chips
Neurons
NoC-based deep neural network accelerators
On-chip communication
performance evaluation
resource-constrained embedded devices
Space exploration
system-on-chip
biblio
Detecting and Mitigating Low-and-Slow DoS Attacks in NoC-based MPSoCs
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
network on chip security
Scalability
resilience
Resiliency
Metrics
computer network security
Denial of Service (DoS) Attack
denial-of-service attacks
Distributed Monitoring
internet
Internet of Things
low-and-slow DoS attack
multiprocessing systems
MultiProcessor Systems-on-Chip
multisource attacks
Muti-Processor System on Chip (MPSoC)
network attack
Network on Chip (NoC)
network-on-chip
NoC
NoC-based MPSoC
NoC-based MPSoC architectures
biblio
An Adaptive Routing Scheme Based on Q-learning and Real-time Traffic Monitoring for Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
network on chip security
Scalability
resilience
Resiliency
Metrics
adaptive routing scheme
C-XY routing
computer architecture
dynamical Q-learning routing approach
dynamical routing
dynamical routing schemes
DyXY routing
Heuristic algorithms
learning (artificial intelligence)
monitor
Monitoring
network congestion
network routing
network-on-chip
NoC
optimisation
packet transmission
performance optimization
Prediction algorithms
q-learning
real-time
real-time systems
Routing
telecommunication traffic
traffic load congestion
traffic monitoring
biblio
A hierarchical approach to self-test, fault-tolerance and routing security in a Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
network on chip security
Scalability
resilience
Resiliency
Metrics
associated physical channels
bus interconnects
chip multiprocessors
communication efficiency
computer network reliability
computer network security
deadlock situation
deadlock-free properties
denial-of-service attacks
external source
fault data
fault tolerant computing
fault-information
fault-tolerance aspects
fault-tolerant routing
flit-switching
hierarchical approach
internet
local processing element
local router
local self-test manager
malformed packets
malicious denial-of-service attack
malicious external agent
microprocessor chips
multiprocessing systems
network bandwidth
network-on-chip
NoC
on-chip networks
packet switching
packet-switching
power virus
routing agent
routing security
security concerns
sorting-based algorithm
telecommunication network routing
test algorithms
two-tier approach
two-tier solution
virtual channel flow control
virtual channels
biblio
Test methodology for detecting short-channel faults in network on- chip networks using IOT
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
network on chip security
Scalability
resilience
Resiliency
Metrics
Aerospace electronics
computer architecture
computing-intensive data processing
Conferences
Cryptography
data encryption
Data protection
Data Security
Encoders/decoders
fault diagnosis
Integrated circuit interconnections
integrated circuit reliability
integrated circuit testing
interconnection networks
Internet of Things
IoT
Monitoring
network on chip
network on- chip networks
network routing
network-on-chip
network-on-chip analysis machine
NoC
Power demand
routers networks
Routing
short-channel fault detection
biblio
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
bit shuffling mechanism
Buffer storage
computer architecture
cryptographic modules
Cryptography
Degradation
denial of service attack
Hardware
hardware security issues
hardware trojan
Router Architecture
performance evaluation
integrated circuit design
microprocessor chips
MPSoC
multiprocessing systems
multiprocessor system on chips
network-on-chip
NoC
performance degradation Hardware Trojan attacks
run time mitigation
security
semiconductor design
system-on-chip
Trojan horses
biblio
Hardware-Assisted Security in Electronic Control Units: Secure Automotive Communications by Utilizing One-Time-Programmable Network on Chip and Firewalls
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
advanced driver assistance systems
authentication
automotive communications
automotive controller area network-bus communications
automotive electronics
Automotive engineering
controller area networks
cyber-enabled automotive system
data privacy
driver information systems
electronic control units
enjoyable driving
firewalls
Firewalls (computing)
Hardware
hardware firewalling
hardware-assisted security
network-on-chip
off-chip networking techniques
on-chip network physical isolation
one-time-programmable network
Secure Automotive Communications
secure execution environments
smart automotive technologies
software-dominated enhancements
system-level countermeasures
system-on-chip
system-wide cryptographic techniques
threat models
Trusted Electronic Control Units
vehicle-to-vehicle communications
biblio
Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
attack efficiency
cache activity
cache line
cache location
cache memories
cache storage
computer architecture
Cryptography
earthquake attack
Earthquakes
encryption
Glass
microprocessor chips
MPSoC configurations
MPSoC Glass
multiprocessing systems
network-on-chip
Network-on-Chip communication structure
NoC
on-chip connectivity
optimized differential cache-collision attacks
optimized variant
programming flexibility
security concerns
Security NoC
system-on-chip
Systems-on-Chips
timing
Timing attack
timing measurements
Timing Side-channel Attack
biblio
A New Hardware Logic Circuit for Evaluating Multi-Processor Chip Security
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
benchmark test set
communication performance optimization
defense strategies
Integrated circuit interconnections
inter-core interconnection method
invasive software
logic circuits
manufacturing processes
multiprocessing systems
multiprocessor chip security
network throughput reduction
network-on-chip
new hardware logic circuit
NoC
NoC hardware security
NoC power consumption
NoC vulnerability
on-chip systems
replay-type hardware Trojan
research hotspots
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