File
CRII: SaTC: Robust Design-for-Security (DFS) Architecture for Enabling Trust in Integrated Circuits (IC) Manufacturing and Test
Submitted by Ujjwal Guin on October 21st, 2019
File
A Key Update Scheme for Side-Channel Attack Mitigation
Submitted by Fareena Saqib on October 21st, 2019
File
Side-Channel Analysis and Resiliency Targeting Accelerators
Submitted by David Kaeli on October 17th, 2019
File
SaTC: TTP: Medium: Collaborative: RESULTS: Reverse Engineering Solutions on Ubiquitous Logic for Trustworthiness and Security
Submitted by Yier Jin on October 17th, 2019
File
SaTC: Core: Medium: Protecting Confidentiality and Integrity of Deep Neural Networks against Side-channel and Fault Attacks
Submitted by Yunsi Fei on October 17th, 2019
File
Parameter Obfuscation: A Novel Methodology for the Protection of Analog Intellectual Property
Ioannis Savidis Submitted by Ioannis Savidis on October 17th, 2019
File
HISA Hardware Isolation-based Secure Architecture for CPU-FPGA Heterogenous Systems
Submitted by Sheng Wei on October 17th, 2019
File
Data Oblivious ISA Extensions for Side Channel-Resistant and High-Performance Computing
Submitted by Christopher Fletcher on October 17th, 2019
File
Computationally Enabled Robust, Low-Power True Random Number Generation
Submitted by Visvesh Sathe on October 17th, 2019
File
CAREER: Utilizing Principles of Energy Recovery Computing for Low-Energy and DPA-Resistant IoT Devices
Submitted by Himanshu Thapliyal on October 17th, 2019
Subscribe to Hardware Security Design