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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
timing
biblio
Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs
Submitted by
grigby1
on Fri, 05/15/2020 - 12:30pm
pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
attack efficiency
cache activity
cache line
cache location
cache memories
cache storage
computer architecture
Cryptography
earthquake attack
Earthquakes
encryption
Glass
microprocessor chips
MPSoC configurations
MPSoC Glass
multiprocessing systems
network-on-chip
Network-on-Chip communication structure
NoC
on-chip connectivity
optimized differential cache-collision attacks
optimized variant
programming flexibility
security concerns
Security NoC
system-on-chip
Systems-on-Chips
timing
Timing attack
timing measurements
Timing Side-channel Attack
biblio
Efficient Timing Channel Protection for Hybrid (Packet/Circuit-Switched) Network-on-Chip
Submitted by
grigby1
on Fri, 05/15/2020 - 12:29pm
pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
channel attacks
circuit switching
circuit switching NoC
combined hybrid routers
conventional hybrid router
covert timing channel
hybrid network-on-chip
hybrid NoC
Integrated circuit modeling
MP-SoC
multiprocessing systems
multiprocessor system-on-chip
network routing
network transmission
network-on-chip
packet switching
packet switching NoC
packet-circuit-switched
security in NoC
Separate interface Hybrid
side-channel attacks
Switching circuits
system security policy
TDM
Throughput
timing
timing channel
timing channel protection
timing characteristics
timing side channel
biblio
Towards the formal verification of security properties of a Network-on-Chip router
Submitted by
grigby1
on Fri, 05/15/2020 - 12:29pm
pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
Cryptography
formal verification
Hardware
integrated circuit design
IP networks
model checking
multiprocessing systems
MultiProcessors Systems-on-Chip
network routing
network-on-chip
Network-on-Chip router
NoC routing architectures
Routing
security
timing
biblio
Security Network On-Chip for Mitigating Side-Channel Attacks
Submitted by
aekwall
on Mon, 05/11/2020 - 11:08am
security of data
Scalability
learning (artificial intelligence)
Resiliency
pubcrawl
Metrics
machine learning
physical interaction
system-on-chip
system security
sensors
Attack detection
timing
Hardware Security
side-channel attacks
integrated circuit design
data analysis
malicious activity
integrated circuits
network-on-chip
active attack
advance invasive attacks
advance noninvasive attacks
advanced technology nodes
attack-specific countermeasures
compromised device
contemporary hardware threats
design complexity
electromagnetic analysis attacks
electromagnetic interference
hardware security threats
high-confidence security network on-chip
individual threats
machine learning security IC
malicious physical interference
modern ICs
multiple countermeasures
on-chip distribution networks
On-chip power delivery
on-chip voltage variations
operating device-under-attack
robust confidence security network on-chip
security networks
Side-channel attack
side-channel attack mitigation
strict performance requirements
trained ML ICs
network on chip security
biblio
APT Attack Situation Assessment Model Based on optimized BP Neural Network
Submitted by
grigby1
on Fri, 05/08/2020 - 2:42pm
security of data
Training
Predictive models
security
Neural networks
pubcrawl
policy-based governance
collaboration
network security
Trojan horses
neural nets
Metrics
advanced persistent threat
APT
Backpropagation
BP Neural Network
adaptive genetic algorithm
Attack Path
attack situation assessment model
genetic algorithms
neural network
security situation
Situation Prediction
timing
Training samples
Neural Network Security
biblio
A Hierarchical Approach to Self-Timed Circuit Verification
Submitted by
aekwall
on Mon, 03/16/2020 - 10:39am
Resiliency
pubcrawl
Computational modeling
Iterative methods
Logic gates
timing
Scalability
Predictive Metrics
Compositionality
Wires
Integrated circuit modeling
hardware description languages
scalable verification
Theorem Proving
ACL2 theorem prover
arbitrated merge
asynchronous circuit modeling
asynchronous circuit verification
combinational circuits
flip-flops
greatest common divisor
greatest common divisor circuit model
hardware description language
hierarchical verification
iterative self-timed circuits
Latches
link joint model
link-joint style
mechanical theorem proving
non deterministic behavior
self-timed circuit verification
timing circuits
biblio
Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes
Submitted by
aekwall
on Mon, 03/16/2020 - 10:39am
Hardware
Protocols
Resiliency
pubcrawl
Computational modeling
standards
Formal Specification
verification
timing
Scalability
Predictive Metrics
Prototypes
Compositionality
formal verification
Clang
hardware description languages
Object oriented modeling
scalable verification
Computer simulation
design verification
Electronic System Level
semiconductor industry
simulation behavior
Simulation-based Verification
SystemC
SystemC language
SystemC VP
SystemC-based virtual prototypes
systems analysis
TLM
TLM-2.0 rules
Transaction Level Modeling framework
Virtual Prototype
virtual prototyping
biblio
Adaptive Network Management for Safety-Critical Systems
Submitted by
aekwall
on Mon, 03/09/2020 - 11:13am
security
computer network security
Scalability
telecommunication traffic
computer network management
software defined networking
Resiliency
pubcrawl
Routing
optimization
optimisation
telecommunication network routing
software-defined networking
Bandwidth
resilience
Safety
timing
computer network reliability
Device-to-device communication
adaptive network management
complex network configurations
Dijkstra algorithm
fault diagnosis
optimization algorithm
Safety-Critical Systems
Security Heuristics
predictability
biblio
Feasibility of a Keystroke Timing Attack on Search Engines with Autocomplete
Submitted by
grigby1
on Tue, 01/28/2020 - 2:36pm
autocomplete
browser
Browsers
computer network security
HTTP requests
Human behavior
Human Factors
hypermedia
information leakage measurement
keyboard input events
Keyboards
keylogging
keylogging side channel attack
keystroke analysis
keystroke timing attack
Metrics
Mutual information
network traffic
packet inter-arrival times
Presses
pubcrawl
search engine
search engines
search predictions
Servers
Side Channel
telecommunication traffic
timing
Traffic analysis
transport protocols
user query input field
Vulnerability
website
Web sites
biblio
Keystroke Based User Authentication Using Modified Differential Evolution
Submitted by
grigby1
on Tue, 01/28/2020 - 2:36pm
Anomaly Detection
authentication
Human behavior
Human Factors
keystroke analysis
keystroke dynamics
Metrics
Modified Differential Evolution
password
Presses
pubcrawl
Subspace Anomaly Detection
Task Analysis
timing
Training
user authentication
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