timing

biblio

Towards Protection Mechanisms for Secure and Efficient CAN Operation

Submitted by aekwall on Mon, 09/21/2020 - 3:46pm

automobiles
Automotive engineering
computer network security
telecommunication traffic
authorisation
real-time systems
Resiliency
pubcrawl
composability
Protocols
Industry 4.0
privacy
authentication
Cyber Attacks
cyber-physical systems
error detection
timing
Clocks
security solutions
controller area networks
CAN bus
access controller
automotive security
broadband services
CAN data-link layer
CAN Security
efficient CAN operation
fault confinement mechanism
iterative research
message priority
numerous proposed solutions
protection mechanisms
real-time message deliverability
secure CAN operation
confinement

biblio

AIS Transmission Data Quality: Identification of Attack Vectors

Submitted by grigby1 on Fri, 08/28/2020 - 12:02pm

AIS
AIS data
AIS networks
Artificial Intelligence
Attack vectors
automatic identification system
Coast Guard
collision avoidance
conceptual countermeasures
data quality
Europe
governments
Human behavior
legislation
marine communication
marine navigation
maritime sector
obstacle avoidance
potential attack vectors
Protocols
pubcrawl
Receivers
resilience
Resiliency
Scalability
security
security of data
Signal resolution
standards
state agencies
timing
transmission data quality
Vectors

biblio

Optimal Timing in Dynamic and Robust Attacker Engagement During Advanced Persistent Threats

Submitted by grigby1 on Fri, 08/07/2020 - 3:58pm

security
pubcrawl
Human behavior
resilience
Resiliency
Scalability
sensors
Games
Metrics
advanced persistent threat
APT
Robustness
Silicon
timing
Markov processes
APT attack
attacker engagement
Markov Decision Process
Stackelberg game

biblio

Detection of Covert Timing Channels with Machine Learning Methods Using Different Window Sizes

Submitted by grigby1 on Thu, 07/16/2020 - 12:17pm

composability
Compositionality
computer network security
covert channels
covert timing channel
data packets
feature extraction
hidden data
information security
learning (artificial intelligence)
Linux
machine learning
machine learning methods
network steganography
Protocols
pubcrawl
resilience
Resiliency
Scalability
TCPIP
telecommunication channels
timing
Vectors
window sizes

biblio

Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs

Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm

pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
attack efficiency
cache activity
cache line
cache location
cache memories
cache storage
computer architecture
Cryptography
earthquake attack
Earthquakes
encryption
Glass
microprocessor chips
MPSoC configurations
MPSoC Glass
multiprocessing systems
network-on-chip
Network-on-Chip communication structure
NoC
on-chip connectivity
optimized differential cache-collision attacks
optimized variant
programming flexibility
security concerns
Security NoC
system-on-chip
Systems-on-Chips
timing
Timing attack
timing measurements
Timing Side-channel Attack

biblio

Efficient Timing Channel Protection for Hybrid (Packet/Circuit-Switched) Network-on-Chip

Submitted by grigby1 on Fri, 05/15/2020 - 12:29pm

pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
channel attacks
circuit switching
circuit switching NoC
combined hybrid routers
conventional hybrid router
covert timing channel
hybrid network-on-chip
hybrid NoC
Integrated circuit modeling
MP-SoC
multiprocessing systems
multiprocessor system-on-chip
network routing
network transmission
network-on-chip
packet switching
packet switching NoC
packet-circuit-switched
security in NoC
Separate interface Hybrid
side-channel attacks
Switching circuits
system security policy
TDM
Throughput
timing
timing channel
timing channel protection
timing characteristics
timing side channel

biblio

Towards the formal verification of security properties of a Network-on-Chip router

Submitted by grigby1 on Fri, 05/15/2020 - 12:29pm

pubcrawl
network on chip security
Scalability
Resiliency
resilience
Metrics
Cryptography
formal verification
Hardware
integrated circuit design
IP networks
model checking
multiprocessing systems
MultiProcessors Systems-on-Chip
network routing
network-on-chip
Network-on-Chip router
NoC routing architectures
Routing
security
timing

biblio

Security Network On-Chip for Mitigating Side-Channel Attacks

Submitted by aekwall on Mon, 05/11/2020 - 11:08am

security of data
Scalability
learning (artificial intelligence)
Resiliency
pubcrawl
Metrics
machine learning
physical interaction
system-on-chip
system security
sensors
Attack detection
timing
Hardware Security
side-channel attacks
integrated circuit design
data analysis
malicious activity
integrated circuits
network-on-chip
active attack
advance invasive attacks
advance noninvasive attacks
advanced technology nodes
attack-specific countermeasures
compromised device
contemporary hardware threats
design complexity
electromagnetic analysis attacks
electromagnetic interference
hardware security threats
high-confidence security network on-chip
individual threats
machine learning security IC
malicious physical interference
modern ICs
multiple countermeasures
on-chip distribution networks
On-chip power delivery
on-chip voltage variations
operating device-under-attack
robust confidence security network on-chip
security networks
Side-channel attack
side-channel attack mitigation
strict performance requirements
trained ML ICs
network on chip security

biblio

APT Attack Situation Assessment Model Based on optimized BP Neural Network

Submitted by grigby1 on Fri, 05/08/2020 - 2:42pm

security of data
Training
Predictive models
security
Neural networks
pubcrawl
policy-based governance
collaboration
network security
Trojan horses
neural nets
Metrics
advanced persistent threat
APT
Backpropagation
BP Neural Network
adaptive genetic algorithm
Attack Path
attack situation assessment model
genetic algorithms
neural network
security situation
Situation Prediction
timing
Training samples
Neural Network Security

biblio

A Hierarchical Approach to Self-Timed Circuit Verification

Submitted by aekwall on Mon, 03/16/2020 - 10:39am

Resiliency
pubcrawl
Computational modeling
Iterative methods
Logic gates
timing
Scalability
Predictive Metrics
Compositionality
Wires
Integrated circuit modeling
hardware description languages
scalable verification
Theorem Proving
ACL2 theorem prover
arbitrated merge
asynchronous circuit modeling
asynchronous circuit verification
combinational circuits
flip-flops
greatest common divisor
greatest common divisor circuit model
hardware description language
hierarchical verification
iterative self-timed circuits
Latches
link joint model
link-joint style
mechanical theorem proving
non deterministic behavior
self-timed circuit verification
timing circuits

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Cyber-Physical Systems Virtual Organization

Fostering collaboration among CPS professionals in academia, government, and industry

timing

Towards Protection Mechanisms for Secure and Efficient CAN Operation

AIS Transmission Data Quality: Identification of Attack Vectors

Optimal Timing in Dynamic and Robust Attacker Engagement During Advanced Persistent Threats

Detection of Covert Timing Channels with Machine Learning Methods Using Different Window Sizes

Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs

Efficient Timing Channel Protection for Hybrid (Packet/Circuit-Switched) Network-on-Chip

Towards the formal verification of security properties of a Network-on-Chip router

Security Network On-Chip for Mitigating Side-Channel Attacks

APT Attack Situation Assessment Model Based on optimized BP Neural Network

A Hierarchical Approach to Self-Timed Circuit Verification