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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
field programmable gate arrays
biblio
Reconfigurable Architecture to Speed-up Modular Exponentiation
Submitted by
grigby1
on Mon, 12/30/2019 - 1:18pm
batch multiplication
Clocks
computationally intensive cryptographic operations
computer architecture
Cryptography
Diffie-Hellman key pair
Diffie-Hellman like protocols
digital arithmetic
exponentiation
field programmable gate arrays
FPGA
frequency 200.0 MHz
Hardware
hardware architecture
modular exponentiation
Modular Multiplication
Pre-computation techniques
pseudorandom number generator
pubcrawl
public key cryptography
Random access memory
random number generation
Reconfigurable Architecture
reconfigurable architectures
Resiliency
RSA protocols
Scalability
Xilinx Virtex 7 FPGA
biblio
Area Constraint Aware Physical Unclonable Function for Intelligence Module
Submitted by
grigby1
on Mon, 12/09/2019 - 1:01pm
area constraint aware physical unclonable function
area constraint aware PUF
artificial intelligence technology
Artificial Neural Networks
authentication
authentication techniques
circuit area
composability
Compositionality
computational intelligence
Cryptography
edge computing
field programmable gate arrays
Hamming distance
Hardware
Hardware Security
intelligence module
IoT devices
neural network
Neurons
NN
Physical Unclonable Function
physical unclonable functions
pubcrawl
PUF performance evaluation
security countermeasures
security of IoT device
Table lookup
biblio
A Secure Voice Channel using Chaotic Cryptography Algorithm
Submitted by
aekwall
on Mon, 11/25/2019 - 1:09pm
field programmable gate arrays
Cryptography
encryption
Receivers
telecommunication security
eavesdropping
Resiliency
pubcrawl
composability
Ciphers
Predictive Metrics
chaotic communication
asynchronous communication
chaotic cryptographic algorithm
chaotic cryptography
chaotic cryptography algorithm
chiper feedback
Cipher feedback mode
communicaiton channel prototype
decryption process
encrypted channel
encryption process
encryption-decription cycle
FPGA Spartan-3
high processing speed
nonecrypted channel
secure voice channel
secure voice communications channel
secured channel
secured communication channel
Spartan-3 FPGA board
time 202.0 mus
unwanted eavesdropping
voice communication
voice messages
biblio
Hardware Implementation of A Chaotic Pseudo Random Number Generator Based on 3D Chaotic System without Equilibrium
Submitted by
aekwall
on Mon, 11/25/2019 - 1:09pm
field programmable gate arrays
Cryptography
Hardware
embedded systems
Resiliency
pubcrawl
composability
Mathematical model
Generators
random number generation
Predictive Metrics
chaotic communication
3D chaotic flows
3D chaotic system
chaotic based digital systems
chaotic behaviors
chaotic dynamics
chaotic pseudorandom number generator
cryptography systems
deterministic chaotic systems
digital communication
digital communication systems
dynamical behavior
Dynamical Systems
Hardware Implementation
lightweight systems
low computational overhead
low-cost chaotic hardware
low-cost hardware platforms
simple nonlinear systems
three-dimensional chaotic flows
Three-dimensional displays
chaotic cryptography
biblio
Realization of System Verification Platform of IoT Smart Node Chip
Submitted by
grigby1
on Tue, 11/12/2019 - 3:29pm
automobiles
chip design cycle
collaboration
composability
Compositionality
design cost reduction
efficient verification platform
field programmable gate arrays
formal verification
FPGA
FPGA-based prototype verification
Internet of Things
IoT node
IoT smart node chip
large scale integrated circuits
policy-based governance
privacy
protocol verification
Protocols
Prototypes
pubcrawl
simulation verification
system verification
system verification platform
Systems Simulation
transmission protocol
Wireless fidelity
biblio
Formal Verification Technology for Asynchronous Communication Protocol
Submitted by
grigby1
on Tue, 11/12/2019 - 3:29pm
aerospace FPGA software products
assert
asynchronous communication
asynchronous communication protocol
blind spots
Clocks
collaboration
complete verification process
composability
Compositionality
field programmable gate arrays
formal verification
formal verification technology
policy-based governance
privacy
process control
Product design
product design quality
property
protocol verification
Protocols
PSL
pubcrawl
Software
traditional simulation method
UART communication
verification work efficiency
biblio
Hardware Implementation of Dynamic Key Value Based Stream Cipher Using Chaotic Logistic Map
Submitted by
grigby1
on Tue, 10/08/2019 - 3:44pm
asymmetric key chaos based cryptography
binary sequence
binary sequences
chaos
Chaos based cryptography
chaotic logistic map
Ciphers
dynamic key value based stream cipher
embedded systems
field programmable gate arrays
Field programmable gated array
FPGA device
frequency 62.2 MHz
Hardware
Hardware Security
hardware-based embedded system
Human behavior
key scheduling
key stream
logistic map
Logistics
Metrics
NIST statistical
nonrecursive key
private key cryptography
PRNG
pseudorandom number generation
pseudorandom sequence generation
pubcrawl
public key cryptography
random key generation
random number generation
Random sequences
randomness tests
resilience
Resiliency
Scalability
stream cipher
symmetric key chaos based cryptography
Thermal analysis
Verilog HDL
X-power
Xilinx device
biblio
Lightweight Security Protocol for Chipless RFID in Internet of Things (IoT) Applications
Submitted by
grigby1
on Wed, 10/02/2019 - 2:02pm
BASYS 2 FPGA board based platform
broader IoT framework
Chipless RFID
chipless RFID system
chipless RFID tag based system
Cryptographic Protocols
Databases
field programmable gate arrays
Human behavior
Human Factors
Internet of Things
IoT
lightweight collision free algorithm
lightweight security protocol
privacy
Protocols
pseudorandom number generator
pubcrawl
radiofrequency identification
random number generation
resilience
Resiliency
RFID
RFID based communication
RFID tags
RFIDs
Secuity
security
tag/reader anonymity
biblio
FPGA-oriented moving target defense against security threats from malicious FPGA tools
Submitted by
aekwall
on Mon, 09/09/2019 - 9:48am
security of data
field programmable gate arrays
FPGA
Hardware
security
Table lookup
Resiliency
pubcrawl
Trojan horses
security threats
Hardware Security
Scalability
Benchmark testing
moving target defense
defense lines
FOMTD
FPGA configuration
FPGA design suite
FPGA emulation results
FPGA hardware-software providers
FPGA security
FPGA users
FPGA-oriented MTD method
hardware trojan
malicious FPGA tools
moving target defense principle
reverse engineering
target defense
Xilinx
Predictive Metrics
biblio
Zynq FPGA Based System Design for Video Surveillance with Sobel Edge Detection
Submitted by
aekwall
on Mon, 08/12/2019 - 8:46am
ADAS
analog composite video interface
analog CVBS
camera
Cameras
computer architecture
computer vision
Decoding
deep learning
deep video
edge detection
edge detection filter
field programmable gate arrays
FPGA
Hardware
HDMI-MIPI CSI
high speed serial interfaces
image classification
Image edge detection
image filtering
Image resolution
industrial automation
input composite video decoding
input composite video surveillance
learning (artificial intelligence)
live traffic analysis
Metrics
pubcrawl
Reconfigurability
Resiliency
Scalability
security
Sobel edge detection
Streaming media
surveillance
Surveillance systems and ARM processor
Thermal Imaging
VGA
video coding
video interface
video streaming
video surveillance
Xilinx ZC702 platfor
ZC702
Zynq FPGA based system design
Zynq-7000
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