The objective of this research is to develop an atomic force microscope based cyber-physical system that can enable automated, robust and efficient assembly of nanoscale components such as nanoparticles, carbon nanotubes, nanowires and DNAs into nanodevices. The proposed approach is based on the premise that automated, robust and efficient nanoassembly can be achieved through tip based pushing in an atomic force microscope with intermittent local scanning of nanoscale components. In particular, in order to resolve temporally and spatially continuous movement of nanoscale components under tip pushing, we propose the combination of intermittent local scanning and interval non-uniform rational B-spline based isogeometric analysis in this research. Successful completion of this research would lead to foundational theories and algorithmic infrastructures for effective integration of physical operations (pushing and scanning) and computation (planning and simulation) for robust, efficient and automated nanoassembly. The resulting theories and algorithms will also be applicable to a broader set of cyber physical systems. If successful, this research will lead to leap progress in nanoscale assembly, from prototype demonstration to large-scale manufacturing. Through its integrated research, education and outreach activities, this project will provide advanced knowledge in cyber-physical systems and nanoassembly for students from high schools to graduate schools and will increase domestic students? interest in science and engineering and therefore strengthen our competitiveness in the global workforce.

The objective of this research is to develop an atomic force microscope based cyber-physical system that can enable automated, robust and efficient assembly of nanoscale components such as nanoparticles, carbon nanotubes, nanowires and DNAs into nanodevices. The approach in this project is based on the premise that automated, robust and efficient nanoassembly can be achieved through tip based pushing in an atomic force microscope with intermittent local scanning of nanoscale components. In particular, in order to resolve temporally and spatially continuous movement of nanoscale components under tip pushing, the research is exploring the combination of intermittent local scanning and interval non-uniform rational B-spline based isogeometric analysis in this research. Successful completion of this research is expected to lead to foundational theories and algorithmic infrastructures for effective integration of physical operations (pushing and scanning) and computation (planning and simulation) for robust, efficient and automated nanoassembly. The resulting theories and algorithms will also be applicable to a broader set of cyber physical systems. If successful, this research will lead to leap progress in nanoscale assembly, from prototype demonstration to large-scale manufacturing. Through its integrated research, education and outreach activities, this project is providing experiences and understanding in cyber-physical systems and nanoassembly for students from high schools to graduate schools. The goal is to increase interest in science and engineering among domestic students and therefore strengthen our competitiveness in the global workforce.

The objective of this research is to develop non-volatile computing devices, which allow the power source to be cut off at any time, and yet resume regular operation without loss of information when the power comes back. The approach is to replace all critical memory components with non-volatile units so that computing state is maintained over power interruptions. The advancement in new Flash memory devices makes this approach feasible by enabling low-voltage program/erase (P/E) around ±2V and a long (projected >1016) cycling endurance to be integrated into CMOS technology. This research effort seeks to establish a new paradigm of computing where non-volatile memory units are used pervasively to enhance reliability against power source instability, energy-efficiency, and security. The non-volatile computing devices are especially useful for embedded cyber-physical systems enabling long running computations and data collection even with unreliable power sources. The technologies developed from this project can also benefit conventional architecture in its power optimization and internal security code generation. The project is a close collaboration between computer architecture and CMOS technology development groups, where all levels in the design hierarchy will be visited for system and technology evaluation. This project integrates its research efforts with education by developing an undergraduate and Master curriculum that spans over the vertical design hierarchy in microprocessors. This vertical education will better prepare future work force in tackling tremendous design challenges spanning many layers of microprocessors. The results from this project will be made widely available to both industry and academia.