FPGA

biblio

Horizontal Correlation Analysis of Elliptic Curve Diffie Hellman

Submitted by aekwall on Mon, 02/15/2021 - 3:57pm

field programmable gate arrays
FPGA
Scalability
Internet of Things
Hardware
Cryptographic Protocols
Resiliency
pubcrawl
Metrics
Correlation
public key cryptography
Elliptic curve cryptography
Elliptic curves
finite element analysis
correlation methods
Secret key
IoT systems
AES
Artix-7 FPGA
chipwhisperer
correlation power analysis
crypto algorithm
CW toolchain
distributed entities
ECDH
elliptic curve diffie hellman
Elliptic Curve Diffie Hellman key exchange protocol
HCPA
Horizontal Correlation Analysis
Horizontal Correlation Power Analysis
in-field sensors
key guess
maximum correlation
NewAE Technologies
open source toolchain
potential threat
power traces
revolutionary technology transition
secure connectivity
side channel analysis
side-channel leaks
simple power analysis
word length -128.0 bit

biblio

FPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem

Submitted by grigby1 on Fri, 01/22/2021 - 12:52pm

chaotic cryptography
pubcrawl
4-dimension chaotic system
chaotic communication
chaotic cryptosystem
chaotic cryptosystem solution
computer network security
Cryptographic Protocols
Cryptography
data phase transfer
DH-HEMTs
field programmable gate arrays
FPGA
FPGA implementation
IKE
IKE protocol
internet
Internet key exchange protocol
IPsec
IPSec protocol
keys phase exchange
man in the middle attack
network communication domain
network protocol
Protocols
SA
securing communications
security association attack
Synchronization
word length 128 bit

biblio

Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body

Submitted by grigby1 on Fri, 01/22/2021 - 12:50pm

chaotic cryptography
pubcrawl
asymmetric cryptography method
chaotic communication
chaotic signal simulation
chaotic synchronization
Cryptography
dynamic systems
Dynamical Systems
encryption circuit
field programmable gate arrays
FPGA
Hopfield neural nets
Hopfield neural networks
human body
information security
Neural networks
random number generation
random number sequence
reconfigurable architectures
reconfigurable hardware
synchronisation
Synchronization

biblio

Efficient Reed-Muller Implementation for Fuzzy Extractor Schemes

Submitted by aekwall on Mon, 01/18/2021 - 10:34am

field programmable gate arrays
FPGA
Scalability
Cryptography
Internet-of-Things
security
Table lookup
Resiliency
pubcrawl
Metrics
counterfeiting
Decoding
fuzzy set theory
security problem
electronic devices
error correction codes
PUF
physical unclonable functions
Distributed Applications
Hamming distance
attack models
area constraints
delay constraints
efficient Reed-Muller implementation
fuzzy extraction scheme
fuzzy extractor schemes
fuzzy-extractor
immunity
intrinsic hardware security
medium-range FPGA device
physical tampering
PUF circuits
PUF implementations
Reed-Muller
Reed-Muller codes
Reed-Muller ECC design
responses stability
Fuzzy Cryptography

biblio

RISC-V FPGA Platform Toward ROS-Based Robotics Application

Submitted by grigby1 on Thu, 12/17/2020 - 1:01pm

Cloud Computing
cloud-based FPGA environment
embedded systems
field programmable gate arrays
FPGA
Human behavior
Human Factors
instruction set computer
local FPGA platform
microprocessor chips
open source community members
open source operating system
open standard instruction set architecture
policy-based governance
pubcrawl
reduced instruction set computing
resilience
Resiliency
RISC-V
RISC-V CPU architecture
RISC-V foundation
RISC-V FPGA platform
RISC-V processor
Robot Operating System
robot operating systems
robotics system
robots
ROS
ROS-based Robotics application
security
super computing field

biblio

High Performance Data Encryption with AES Implementation on FPGA

Submitted by grigby1 on Tue, 12/01/2020 - 12:46pm

AES
AES encryption algorithm
AES implementation
Big Data
BIGDATA
composability
Cryptography
Data Security
encryption
encryption speed
field programmable gate arrays
FPGA
high performance data encryption
high speed
IDS
intrusion detection system
low latency
Pipelines
pubcrawl
Random access memory
resilience
Resiliency

biblio

FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function

Submitted by aekwall on Mon, 11/09/2020 - 12:31pm

composability
Cryptography
field programmable gate arrays
FPGA
FPGA based designs
FPGA based IP protection scheme
FPGA IP obfuscation
hardware obfuscation
IP obfuscation
IP piracy
logic design
Logic gates
logic obfuscation
Oscillators
policy-based governance
pubcrawl
PUF
Resiliency
Ring Oscillator
ring oscillator based physical unclonable function
ring oscillator physical unclonable function

biblio

FPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem

Submitted by aekwall on Tue, 09/08/2020 - 9:12am

computer network security
field programmable gate arrays
FPGA
Cryptographic Protocols
Protocols
Resiliency
pubcrawl
composability
Synchronization
Cryptography
internet
DH-HEMTs
Predictive Metrics
chaotic communication
chaotic cryptography
IPSec protocol
securing communications
IPsec
4-dimension chaotic system
chaotic cryptosystem
chaotic cryptosystem solution
data phase transfer
FPGA implementation
IKE
IKE protocol
Internet key exchange protocol
keys phase exchange
man in the middle attack
network communication domain
network protocol
SA
security association attack
word length 128 bit

biblio

Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body

Submitted by aekwall on Tue, 09/08/2020 - 9:11am

field programmable gate arrays
FPGA
Cryptography
information security
Resiliency
pubcrawl
composability
synchronisation
Synchronization
Neural networks
random number generation
Dynamical Systems
Predictive Metrics
chaotic communication
chaotic cryptography
reconfigurable architectures
asymmetric cryptography method
chaotic signal simulation
chaotic synchronization
dynamic systems
encryption circuit
Hopfield neural nets
Hopfield neural networks
human body
random number sequence
reconfigurable hardware

biblio

High Speed Parallel RC4 Key Searching Brute Force Attack Based on FPGA

Submitted by grigby1 on Fri, 09/04/2020 - 2:36pm

Ciphers
Cryptography
encryption
Hardware
pubcrawl
Force
process control
Human Factors
policy-based governance
field programmable gate arrays
block RAM
Brute force
clock rate
Clocks
field programmable gate array
forecast keying methods
FPGA
frequency 128 MHz
High Speed Parallel RC4 Key Searching Brute Force Attack
key searching speed
key searching unit
main controller
on-chip BRAM
random-access storage
RC4
RC4 algorithm
stream cipher
Xilinx XC3S1600E-4 FPGA device
brute force attacks

1
2
3
4
5
6
7
next ›
last »

Cyber-Physical Systems Virtual Organization

Fostering collaboration among CPS professionals in academia, government, and industry

FPGA

Horizontal Correlation Analysis of Elliptic Curve Diffie Hellman

FPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem

Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body

Efficient Reed-Muller Implementation for Fuzzy Extractor Schemes

RISC-V FPGA Platform Toward ROS-Based Robotics Application

High Performance Data Encryption with AES Implementation on FPGA

FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function

FPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem

Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body

High Speed Parallel RC4 Key Searching Brute Force Attack Based on FPGA