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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
FPGA
biblio
Hardware implementation of Piccolo Encryption Algorithm for constrained RFID application
Submitted by
aekwall
on Mon, 02/10/2020 - 10:44am
IoT
field programmable gate arrays
FPGA
Cryptography
encryption
Internet of Things
telecommunication security
Hardware
Table lookup
IoT applications
smart devices
Resiliency
pubcrawl
composability
security applications
RFID
Throughput
Ciphers
security issues
Predictive Metrics
private information
word length 128.0 bit
Hardware Implementation
hardware resources
lightweight cryptographic algorithms
S-box
lightweight cryptography
128 bits
4 input LUTs
64 bits block size
area optimization
ASIC
constrained RFID application
different design strategies
efficient hardware architecture
Fiestel structure
hardware design
hardware metrics
low resource applications
optimized area
Piccolo Algorithm
piccolo encryption algorithm
piccolo lightweight algorithm
radiofrequency identification
relevant lightweight block ciphers
severe security concerns
supports high speed
Throughput.
tremendous pace
ultra-lightweight applications
variable key size
word length 64.0 bit
word length 80.0 bit
Xillinx
Microelectronics Security
biblio
Research in Fast Modular Exponentiation Algorithm Based on FPGA
Submitted by
grigby1
on Tue, 01/21/2020 - 10:50am
automation
Conferences
Erbium
exponentiation
fast modular exponentiation algorithm
field programmable gate arrays
FPGA
frequency 170.0 MHz
logic design
mechatronics
modular exponentiation
modular exponentiation on large number
Modular Multiplication
Montgomery algorithm
Montgomery modular multiplication
pubcrawl
public key cryptography
public-key algorithm
public-key cryptography
public-key cryptosystem
Q measurement
resilience
Resiliency
Scalability
systolic array
systolic arrays
biblio
Extracting Side-Channel Leakage from Round Unrolled Implementations of Lightweight Ciphers
Submitted by
aekwall
on Mon, 01/20/2020 - 10:59am
advanced encryption standard
AES
AES algorithm
Band-pass filters
Ciphers
combinational logics
Correlation
correlation frequency analysis
Cryptography
edge nodes
encryption
Energy Efficiency
field programmable gate arrays
Filtering
first-order side-channel leakages
FPGA
fully-unrolled datapath
Hardware
improved CFA attack
leakage models
Lightweight Ciphers
lightweight cryptographic algorithms
multiband narrow bandpass filtering techniques
narrow bandpass filtering
optimal leakage models
parallel round-based datapath
PRINCE
pubcrawl
Resiliency
resource constraints
round unrolled implementations
round unrolling
Scalability
side channel analysis
side channel analysis attacks
side channel signatures
side-channel leakage
signal isolation
Signal to noise ratio
signal-to-noise ratio
SIMON
SIMON datapaths
size 45.0 nm
SNR
time domain correlation power analysis
biblio
Performance evaluation of lightweight Block Ciphers in soft-core processor
Submitted by
aekwall
on Mon, 01/20/2020 - 10:59am
AHB bandwidth
Ciphers
CPU performance
Cryptography
encryption
execution time
field programmable gate arrays
FPGA
HIGHT crypto ciphers
Internet of Things
IoT
LBlock crypto ciphers
LED crypto ciphers
LEON3 open source processor
LEON3 processor
light emitting diodes
lightweight block ciphers
lightweight blocks crypto ciphers
Lightweight Ciphers
lightweight cryptography
lightweight cryptography algorithms
microprocessor chips
PICCOLO crypto ciphers
PRESENT crypto ciphers
pubcrawl
Resiliency
RFID devices
Scalability
soft-core processor
Software
Throughput
biblio
Reconfigurable Architecture to Speed-up Modular Exponentiation
Submitted by
grigby1
on Mon, 12/30/2019 - 1:18pm
batch multiplication
Clocks
computationally intensive cryptographic operations
computer architecture
Cryptography
Diffie-Hellman key pair
Diffie-Hellman like protocols
digital arithmetic
exponentiation
field programmable gate arrays
FPGA
frequency 200.0 MHz
Hardware
hardware architecture
modular exponentiation
Modular Multiplication
Pre-computation techniques
pseudorandom number generator
pubcrawl
public key cryptography
Random access memory
random number generation
Reconfigurable Architecture
reconfigurable architectures
Resiliency
RSA protocols
Scalability
Xilinx Virtex 7 FPGA
biblio
Accelerated DDoS Attacks Mitigation using Programmable Data Plane
Submitted by
aekwall
on Wed, 12/18/2019 - 1:24pm
composability
DDoS attack mitigation
ddos mitigation
denial-of-service attacks
FPGA
Human behavior
Metrics
P4
programmable data planes
pubcrawl
resilience
biblio
Realization of System Verification Platform of IoT Smart Node Chip
Submitted by
grigby1
on Tue, 11/12/2019 - 3:29pm
automobiles
chip design cycle
collaboration
composability
Compositionality
design cost reduction
efficient verification platform
field programmable gate arrays
formal verification
FPGA
FPGA-based prototype verification
Internet of Things
IoT node
IoT smart node chip
large scale integrated circuits
policy-based governance
privacy
protocol verification
Protocols
Prototypes
pubcrawl
simulation verification
system verification
system verification platform
Systems Simulation
transmission protocol
Wireless fidelity
biblio
An Improved Cross-Coupled NAND Gates PUF for Bank IC Card
Submitted by
grigby1
on Wed, 09/11/2019 - 1:45pm
composability
FPGA
Metrics
Microelectronics Security
physical unclonable functions
pubcrawl
resilience
Resiliency
system-on-chip
biblio
FPGA-oriented moving target defense against security threats from malicious FPGA tools
Submitted by
aekwall
on Mon, 09/09/2019 - 9:48am
security of data
field programmable gate arrays
FPGA
Hardware
security
Table lookup
Resiliency
pubcrawl
Trojan horses
security threats
Hardware Security
Scalability
Benchmark testing
moving target defense
defense lines
FOMTD
FPGA configuration
FPGA design suite
FPGA emulation results
FPGA hardware-software providers
FPGA security
FPGA users
FPGA-oriented MTD method
hardware trojan
malicious FPGA tools
moving target defense principle
reverse engineering
target defense
Xilinx
Predictive Metrics
biblio
Zynq FPGA Based System Design for Video Surveillance with Sobel Edge Detection
Submitted by
aekwall
on Mon, 08/12/2019 - 8:46am
ADAS
analog composite video interface
analog CVBS
camera
Cameras
computer architecture
computer vision
Decoding
deep learning
deep video
edge detection
edge detection filter
field programmable gate arrays
FPGA
Hardware
HDMI-MIPI CSI
high speed serial interfaces
image classification
Image edge detection
image filtering
Image resolution
industrial automation
input composite video decoding
input composite video surveillance
learning (artificial intelligence)
live traffic analysis
Metrics
pubcrawl
Reconfigurability
Resiliency
Scalability
security
Sobel edge detection
Streaming media
surveillance
Surveillance systems and ARM processor
Thermal Imaging
VGA
video coding
video interface
video streaming
video surveillance
Xilinx ZC702 platfor
ZC702
Zynq FPGA based system design
Zynq-7000
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