Bringing the Multicore Revolution to Safety-Critical Cyber-Physical Systems
Abstract:
Shared hardware resources like caches and translation look aside buffers (TLBs) introduce timing unpredictability for real-time systems. We propose techniques to mitigate unpredictabil- ity for multicore systems. The TLB improves the performance of the system by caching the virtual page to physical frame mapping. But TLBs present a source of unpredictability for real-rime systems. Standard heap allocated regions do not provide guarantees on the TLB set that will hold a particular page translation.
Submitted by Namhoon Kim
on
Abstract:
Shared hardware resources like caches and translation look aside buffers (TLBs) introduce timing unpredictability for real-time systems. We propose techniques to mitigate unpredictabil- ity for multicore systems. The TLB improves the performance of the system by caching the virtual page to physical frame mapping. But TLBs present a source of unpredictability for real-rime systems. Standard heap allocated regions do not provide guarantees on the TLB set that will hold a particular page translation.
Submitted by Namhoon Kim
on