Abstract: Shared hardware resources like caches and memory introduce timing unpredictability for real-time systems. Worst-case execution time (WCET) analysis with shared hardware resources is often so pessimistic that the extra processing capacity of multicore systems is negated. We propose techniques to improve performance and schedulability for multicore systems.

Abstract: Shared hardware resources like caches and translation look aside buffers (TLBs) introduce timing unpredictability for real-time systems. We propose techniques to mitigate unpredictabil- ity for multicore systems. The TLB improves the performance of the system by caching the virtual page to physical frame mapping. But TLBs present a source of unpredictability for real-rime systems. Standard heap allocated regions do not provide guarantees on the TLB set that will hold a particular page translation.